Single-electron devices in silicon

Fabrication techniques

Fabrication of small-scale devices can be done with two basic approaches called ‘bottom-up’ and ‘top-down’. Processes are called bottom-up, when structures are grown in a self-organised manner as opposed to ‘carved out’ from an existing material, using an external design – a top-down approach. Most device fabrication involves both general approaches, in the sense that material is grown bottom-up and shaped by a lithographic technique. Often, these processes are repeated multiple times to build more complicated devices.

In lithography, a resist mask is defined on a chip via local exposure to light or an electron beam that locally alters the chemical properties and enables selective removal of the resist. In a subsequent step, the pattern can then be transferred to the material underneath via etching or metalisation. In both cases, one limiting factor for the minimal feature size is the wavelength of the electrons or light in the exposure step. For example, the optical-light wavelengths in, so-called, optical lithography do not permit a resolution that is required for modern decananometre scale devices, such that industry moved to deep UV techniques for high resolution and mass fabrication. ¹⁹ This technique uses exposure through a physical mask, and is therefore capable of fast mass fabrication of many devices in parallel. Researchers, on the other hand, widely use the slower, but higher resolving, technique of electron beam lithography (EBL). In this process, an electron beam has to write structures one pixel at a time, and parallel fabrication is not possible.^20,21 The gap between laboratory prototypes and industrial scale fabrication can be closed for the next generations of nanotechnology by further improvements of deep UV or multi-beam techniques in EBL.^22,23 In any case, the development of high-resolution lithography techniques will be crucial for further miniaturisation of devices.

Apart from diffraction limitations, lithographic techniques are typically limited by scattering processes in the resist or scattering from the underlying material, that locally affect the chemistry in development.^24,25 Moreover, the ability to remove materials after development in a lift-off or etching step can limit device sizes and spacing. ²⁶ The details of these techniques are, therefore, complex, and depend on the used materials, resist as well as geometry of the written patterns. In this review, I will give only a rough idea of the current resolution limits, and want to remind the reader that the processes cannot necessarily be transferred to other materials, thicknesses or geometries. A rough estimate for the required island size in a single-electron device with room-temperature operation can be extracted from work by Shin et al. ²⁷ to be on the order of few nanometres (see Fig. 12).

Among other efforts to make controllable nanometre scale structures, ²⁸ notable achievements include the work by Cumming et al. ²⁹ in 1995, who fabricated wires made from NiCr with a thickness of 3 nm using EBL. While this length scale is very impressive, it needs to be stressed that the resolution was achieved using ‘proximity-electrons’. Therefore, the pattern was not really written with this resolution in the sense that the beam was not directed to the written area. Instead, the statistical uncertainties of the exposure were exploited to write one particular simple geometry, which makes the transfer to other patterns extremely difficult.

More flexible patterning of sub 10 nm structures using the actual beam was done by Vieu et al. ³⁰ in polymethacrylate (PMMA). This, however, was only possible for single features, while arrays of patterns needed to be spaced by a, so-called, ‘pitch’ of 30 nm. In this work, it also became apparent that the limiting factor lies in the PMMA development rather than the exposure accuracy. Later work, therefore, focused on other resist systems, such as hydrogen silsesquioxane (HSQ), which forms SiO when exposed with an electron beam. ³¹ In HSQ, 7 nm features have been demonstrated, which makes this resist system promising for fabrication of silicon-based devices. ³² Often, the patterning of structures with HSQ is done using a consecutive dry etch process that needs to be highly optimised to transfer the SiO mask from HSQ to the underlying material without loss of resolution. In addition, a double-layer process can be used to liftoff remaining SiO, if necessary. ³³

In 2012, Mirza et al. ³⁴ optimised a dry etch process, such that HSQ lines could be transferred into silicon with a very straight etch profile and therefore no loss of resolution (see Fig. 2). These sub 10 nm width silicon structures could be produced with a ratio of 50:1 in height vs. width, and are therefore an interesting system for the fabrication of the ‘multi-gate transistors’ shown in Fig. 5, e.g. ‘FinFETs’ – a Field Effect Transistor that is used in many modern devices with a channel in the shape of a fin (see Fig. 5, top left).

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Cross section of a silicon device after HSQ patterning and reactive ion etching ³⁴

Another important technique that is used very frequently, e.g. for the fabrication of an insulating layer between the channel and the gate of a transistor, is oxidation. Often insulating layers are fabricated using oxidation of the material that is already on the chip, but it can be beneficial to deposit an oxide that is not native to the used material. In another technique, called ‘Pattern-dependent oxidation’ (PADOX), one can use oxidation in order to introduce strain to an underlying material. This strain is created depending on the profile of the material that is oxidised. In that way, it is possible to fabricate tunnel barriers by oxidising a device on the sides of a very steep trench that was defined using one of the techniques discussed in this section.^35,36

Small-scale effects, random parameter fluctuations and few dopant devices

While the fabrication of small structures is challenging in itself, there are also intrinsic issues with very small, doped devices. One of the important issues is related to the discrete nature of matter. The first doped semiconductor devices could easily be understood in terms of dopant density, because the number of dopants in a channel was very large, and fluctuations were therefore relatively small. At the length scales of today's devices, however, random fluctuations of dopant number and surface effects are a major issue, and can have a big impact on reproducibility of, for example, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). ³⁷

The aspect of surface effects was studied for example in simulations by Nishinohara et al., ³⁸ who found a lowering of the average threshold voltage with decreasing MOSFET size down to a channel length of . The effects of random dopant positioning were studied for example in experiments by Mizuno et al. ³⁷ The authors found Gaussian distributions of dopant density for a Poisson-like implantation profile of dopants in arrays of transistors with channel lengths down to . As a consequence, they also found that the distribution of threshold voltages over many devices with Poisson-like random doping is a Gaussian distribution. For fabrication on an industrial scale, where all devices should switch on in a similar manner, these fluctuations in performance can be an issue.

In later simulations, Asenov et al.^39,40 were able to simulate realistic dopant distributions in a 3D model of smaller MOSFET devices down to including a wide variety of parameter fluctuations, such as surface effects, dielectric environment, trapped charges or interface and line edge roughness. The simulations show increasing threshold voltage deviation with decreasing channel length for different dopant distributions with same average dopant density. This and similar simulation tools were commercialised, such that there are now a number of excellent programmes available and used routinely in industrial process development in order to predict device behaviour at a certain scale, doping density or geometry.

In parallel, there were theoretical efforts to include confinement of charge carriers into the band structure. One example is the band structure in semiconductor nanowires as a function of wire radius from that shows lifting of valley degeneracies, and can lead to an increased bandgap for decreasing nanowire radius depending on the dielectric environment. ⁴¹

Using the presented tools in this section, it is possible to predict the influence of small-scale effects on device performance. However, to achieve reproducibility, it is also necessary to minimize these parameter fluctuations, especially because the effects become more dominant at small scales. While issues like surface roughness can be solved with improved lithography, etching and resist technologies, random dopant fluctuations will also need to be addressed. This requires more elaborate techniques to deterministically place a fixed number of dopants into a device, rather than the Poisson-like statistical doping that is widely used in industry. ⁴²

Apart from more reproducible conventional devices, deterministic doping techniques could also be used for the fabrication of few or single-dopant devices. ⁴³ In these devices, the semiconductor is used only as a host material for dopant atoms that dominate device properties with respect to, for example, transport or spin-phenomena.^14,44

One approach towards deterministic doping is a modification of the statistical method from industry. The basic idea is to control the dopant location using a mask, while counting dopants in a detector scheme in order to ensure the desired number of dopants is implanted.^45–48 In these approaches, a discrete step in current through the host material is registered when a dopant is implanted, such that the process can be stopped when the desired number of dopants is reached. However, not every ion that is implanted into the material will be activated as a dopant, and instead can end up as an impurity or trapped charge in the oxide. ⁴⁷ Moreover, the technique does not allow for reliable parallel fabrication of many devices on a chip, because dopant implantation is a statistical process that can vary for different devices. This statistical uncertainty is a big disadvantage for the technique, since it limits performance of the fabricated devices through trapped charges, while parallel fabrication can only be done with separate sources or a focused-ion beam. ⁴⁸

Alternatively, there is an approach towards deterministic doping using scanning tunnelling microscopy (STM) in a technique called hydrogen STM-lithography. ⁴⁹ In this process, STM is used to selectively remove hydrogen bonds from a hydrogen-terminated silicon surface (see Fig. 3a). In the next step, the sample is covered with PH molecules, which only bind to the exposed dangling bonds created in the first step. Finally, an annealing step incorporates the phosphor into the silicon surface, which can then be overgrown using molecular beam epitaxy. ⁴⁹ This technique provides phosphorous doping in silicon with a resolution of about and has also been shown in germanium. ⁵⁰ Figure 3 shows an STM picture of the surface with a hydrogen desorption point as well as the finished surface with a dopant.

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Hydrogen STM-lithography: (a) H-terminated silicon surface, with a nm hydrogen desorption point (b) Same area after exposure to PH and annealing ⁴⁹

Fabrication of SETs

Single-electron devices have been fabricated with many different techniques, in different materials and with different geometries, but for operation SETs of all designs require one charge island between two tunnel barriers to the contacts (also called ‘leads’).^{4–6,10,43,51} In that way, charges are confined to the island in terms of classical electrodynamics, and can only escape because of quantum tunneling. Apart from one control gate for the manipulation of the island potential, many designs also introduce the tunnel barriers using additional gates to control the tunnel coupling.

For high-temperature operation with good reproducibility, it is necessary to develop a process without statistical uncertainties and very tight spatial confinement. The development of such a process is currently the main threshold towards commercialisation of single-electron devices for a bigger market, for example, in portable charge sensing applications with high sensitivities. A device would typically require an island size less than in the largest dimension in order to separate on-state and off-state energies further than thermal broadening at room-temperature such that the SET can be switched.^9,36

‘Transport in SETs, pumps and turnstiles’ will discuss how this can be achieved when the quantum confinement of electrons on a small island increases the level spacing. ⁵²

In the first SET devices, tunnel barriers were made from two oxide layers between island/source and island/drain in an aluminium device fabricated with a process called ‘shadow evaporation’. ⁴ In shadow evaporation, one exploits particularities of resist development to fabricate a bridge of resist that is suspended without contact to the chip surface. A metal/oxide/metal junction can then be fabricated when metal is evaporated from an angle, subsequently oxidised and partially covered with a second metal layer that is evaporated from a different angle. Although this process is reproducible, tunnelling rates could be tuned only through the variation of oxide thickness, and charge confinement to an island area of in the first devices was not tight enough for higher temperature operation than . A typical early device built using aluminium shadow evaporation with a large gate, island, source and drain contact is shown in Fig. 4. A similar technique was used by Keller et al. ⁵³ in order to fabricate multiple metal islands in series and use it for charge pumping. In later work, Berman et al. ⁵⁴ measured single-electron transport through an island that was electrostatically defined with top-gates in a GaAs 2D electron gas, with an Al-SET. Fricke et al. ⁵⁵ used a metal SET to read-out transferred charges through a pump that was fabricated in a 2D electron gas using top gates.

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Aluminium SET fabricated with the shadow evaporation technique ⁵⁴

While on-chip sensing with SETs is a very sensitive and useful technique, the implementation of SETs in every day electronics, e.g. as charge sensors, is not possible unless they can be fabricated reproducibly and work at higher temperatures. Owing to the success in miniaturisation and overall process development in the past, this goal is often associated with silicon technology. Silicon SETs have been demonstrated in grown nanowires, ⁵⁶ 2D electron gases ⁵⁷ and in FETs at low temperatures with, for example, polysilicon gates.^58,59 In particular, approaches using FETs could be incorporated into silicon MOS fabrication and therefore fulfil the scalability requirements that could eventually lead to large-scale commercialisation. However, most previous devices made from modified, commercially available FETs do not provide tight enough confinement for room-temperature operation or have reproducibility issues, such that the implementation in every-day electronics is not possible at this stage.

Confinement and reproducibility issues also limit the operation of most structures where strain ⁶⁰ or doping variations ⁶¹ are used to create barriers. Generally, these barriers become increasingly difficult to fabricate in devices that are intended for high-temperature operation, because the spacing between tunnel barriers typically needs to be smaller than and it is not trivial to control strain or doping on such scales. ³⁶

Despite these challenges, Shin et al.^27,36 demonstrated room-temperature operation of devices made from FinFET channels with a steeply etched trench in the center and oxidation-induced strain. In that way, PADOX created self-aligned tunnel barriers on the sides of a gate that was placed around the channel. The island size was determined by a wire radius, as well as the interplay between strain and gate that creates confinement along the wire on the order of . A more detailed discussion of this work will follow in the section ‘High-temperature operation’.

Another way of fabricating SETs is exploiting the electrostatic potential of ionised dopants as charge islands that are located in a non-conductive host silicon to form the tunnel barriers to source and drain. ⁸ Single-dopant devices can be fabricated via STM lithography (see previous section), which is capable of placing dopants with the required resolution but requires improved parallel processing with multiple cantilevers for mass production. ⁶² In addition, it is not possible to build room-temperature SETs with this technique, because the used chemistry does not involve dopants with tight enough confinement potentials. ⁴⁹

As discussed earlier, other approaches focus on low-energy ion implantation through apertures, where single implantation could be reached using in situ detection of implantation events.^47,48 Although this approach is more promising for large-scale production, and can be done for a range of dopants, sufficient resolution for current nanowire/FinFET length scales have not been achieved so far. While the accuracy is limited by the aperture size of , ⁴⁸ which can be improved in the future, the random scattering of dopants in ion-implantation cannot be controlled, such that the resolutions of STM-lithography are not possible.

In conclusion, there is potential in single-dopant devices, but there need to be improved means of fabrication in order to use the technology outside of the laboratory. Therefore, devices based on gates and/or strain seem to be more scalable at this point.

SETs in silicon fin-field-effect transistors

To build reproducible, high-temperature SETs using a technique that is capable of mass-production, one interesting approach employs a FinFET geometry, as shown in Fig. 5, with additional gates. FinFETs feature a horizontally thin and vertically high channel region such that confinement in one dimension is already relatively tight down to few nanometres. ³⁴ For high-temperature SETs, the vertical channel dimension has to be reduced, and tunnel barriers need to be introduced with closely spaced gates or PADOX.

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Schematic of different kinds of multi-gate transistors ⁶³

FinFETs were developed to reduce off-state currents in small-scale transistors, using a geometry, where a gate wraps around several sides of the channel to increase electrostatic control (see Fig. 5). ⁶³ As a result, the current channel can be pinched off from multiple sides simultaneously, as opposed to one side in conventional MOSFETs. While a single wrap-around gate provides excellent electrostatic control, the remaining challenge for SETs with tunable barriers is the fabrication of multiple small gates with tight spacing such that a very small island forms when two gates deplete the channel locally, and one gate creates an island in between. In principle, similar devices can also be built in a different semiconductor, for example, GaAs, but that often comes with the disadvantage of higher costs and/or the need to develop even more new fabrication processes. ⁶⁴

Additional challenges in FinFET geometries, apart from fabrication of narrow gates, include an increasing effect of dopant deactivation with decreasing device size. One contribution to dopant deactivation is diffusion of impurities that were intended as dopants, to the surface. ⁶⁵ The second reason for deactivation of dopants is a dielectric mismatch against traps or dielectric materials, e.g. close to the channel/oxide interface, and the resulting electrostatic effect on the potential landscape. This not only results in a deactivation of dopants close to the surface, for example, in close proximity to charge traps, but can also affect dopants in the bulk of the channel. ⁶⁶ In any case, dopant deactivation causes reduced charge densities and therefore higher resistances in the channels.

The quantity that determines whether a trap or impurity can act as a donor or acceptor is its charging energy (activation energy). This energy needs to be provided in order to free a charge carrier from the donor/acceptor such that it can contribute to conductance. ⁵² The activation energy depends on the dielectric surroundings of the impurity such that it can vary substantially depending on the position of the impurities within the device. In particular for smaller devices, this effect can be significant when the surface to volume ratio becomes larger. ⁶⁷

Björk et al. ⁶⁶ demonstrated the effect of dielectric mismatch for silicon nanowires as a function of radius, and also stressed the importance of gates on all surfaces of a small transistor channel. In a wire with radius coated by its native oxide, the charge density is already 50% lower than in bulk silicon, which shows the dramatic influence of dopant deactivation. Additionally, this illustrates why defect-free oxides and surface effects become increasingly important for decreasing device size. Figure 6 shows a schematic of band-bending, leading to effective shrinking of the conductive channel at the surface of a nanowire owing to surface charges. The carrier density in uniformly doped wires as a function of the remaining electric radius shows the deactivation of dopants owing to increasing dielectric effects with decreasing wire radius.

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(a) Schematic of band bending at the surface of a nanowire. Negative surface traps result in a deactivated region, such that the electrically active region is smaller than the wire radius. (b) Charge carrier density in uniformly doped nanowires as a function of electrical wire radius. ⁶⁶

Limiting the fraction of deactivated dopants is crucial for the performance of small devices, such that the use of clean interfaces with trap free oxides and all around gates is an important issue in fabrication. Mirza et al. ⁶⁸ developed a FinFET design that combines extremely clean oxide layers with very small length scales. The devices were fabricated using top-down lithographic techniques with a negative tone HSQ resist. In the process, the resist gets patterned on top of a silicon on isolator (SOI) wafer by EBL, and then etched with reactive ion etching. ³⁴ In this way, the remaining structure is a ‘junctionless’ etched piece of silicon without material boundaries that can be coated in a high-quality oxide and wrapped in an all around gate forming a ‘junctionless FinFET’ (see Fig. 7a). ⁶⁹ At , the produced devices are highly doped above the Mott-criterion in 3D ( ⁷⁰ ), where a bulk silicon device behaves like a metal. It is impossible to build a transistor in such a bulk material, because of the screening effects in the material. In other words, there is no accessible bandgap close to the Fermi energy, and it is impossible to switch the channel off. ⁷¹ However, since the devices have average channel widths down to , the transport is 1D and the 3D theory is not applicable. The bulk Mott-transition is, therefore, irrelevant for the channels, and the transistor can be gated even at high doping.

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(a) Transmission electron microscope picture of the FinFET cross-section from Mirza et al. ⁶⁸ (b) Resistivity as a function of temperature for different FinFETs. The widths refer to an average over the cross section, where 4 nm, 7 nm and 18 nm correspond to the pictures in (a). (c) Mobility and carrier density from four-point measurements in magnetic fields (Squares: mobility, Circles: carrier density; Green: 4 nm, Red: 7 nm, Blue: 12 nm, Black: 18 nm.) ⁶⁸

At , the limiting process for mobility in these devices was determined to be neutral impurity scattering, which means the effects from surface roughness or trapped charges in the oxide are not dominating the transport properties. ³⁴ When multiple gates are added, it is, therefore, likely that single-charge islands in this system could show unperturbed Coulomb blockade.

In parallel, there is other work on commercially available FinFETs and silicon channels with one gate. Recent work from Lavieville et al. ⁷² and work by Shin et al.^{27, 36} report on room-temperature operation in a silicon channel SET. The devices from Shin et al. were fabricated with PADOX in order to form tunnel barriers in a self-aligned manner in the oxidation and gate fabrication process (see ‘Fabrication techniques’ and ‘High-temperature operation’, Figs. 12 and 13).

Multiple gates for high-temperature SETs have not been reported, but there are efforts towards improved gate fabrication.^73,74

SETs and charge sensing application

The first SETs were fabricated by a shadow evaporation technique in Al. ⁴ They were based on two Josephson junctions (below critical temperature) and a relatively large charge island on the order of . Because of the critical temperature in Al (), these experiments involved single-electron transport for temperatures above the critical value as well as single Cooper pairs at lower temperatures.^4,81

While this early work mostly discussed first-order tunnelling with Coulomb blockade, latter work also focused on co-tunneling effects. ⁸² These effects can involve tunnel processes through multiple states or consecutive tunnelling events of different charges and occur with a probability that is a function of every single process involved. The number of co-tunnelling events is therefore usually only comparable to tunnelling according to the CIM and Coulomb-blockade for strongly coupled systems – for example, for small tunnel barriers. ⁸²

Studies of these effects in a device fabricated from an undoped 7 nm 12 nm 7 nm double barrier heterostructure by DeFranceschi et al. ⁸² are shown in Fig. 8, together with schematics that explain different types of tunnelling events involved.

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DeFranceschi's measurements on a GaAs layer structure forming a pillar with an SET (inset in (f)). (a) schematic drawing of features in a conductance measurement as a function of source-drain and gate-voltage . White regions correspond to conductive regions according to tunnelling in the Coulomb-blockade picture. In the light grey region, transport is possible via elastic co-tunneling, while dark grey denotes inelastic co-tunnelling. (b) and (e) depict the process of tunnelling through an additional excited state (dashed lines in a). Figure (c) and (d) shows elastic and inelastic co-tunnelling processes. Figure (f) shows the data from the experiment ⁸²

Silicon SETs with planar geometry were built from a quantum dot in a two-dimensional electron gas in silicon that was defined through local depletion with top-gates. Angus et al. ⁵⁷ built devices with a island and performed excited state spectroscopy at . They found energy level spacings up to , and therefore demonstrated the confinement in their device. In 2006, Fujiwara et al. ⁵⁹ demonstrated Coulomb blockade at over a large gate range in a MOSFET channel. Figure 9a and b shows the device made from a silicon channel with three poly-silicon gates that are spaced , while Fig. 9c shows the Coulomb-peaks in conductance as a function of the voltage applied to the middle gate at .

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Devices from Fujiwara et al. ⁵⁹ (a) schematic of the device with three local lower gates and one big top-gate. (b) SEM picture of the device without top gate. (c) conductance as a function of gate-voltage in the configuration with the middle gate controlling the quantum dot created by the barriers induced from the other two gates and

More integrated silicon devices were fabricated by Ono et al., ⁸³ who built an inverter using two silicon SETs in an etched silicon structure with PADOX-fabricated barriers operating at and the largest island dimension being . This work shows the aspirations for semiconductor-based SETs, because the quantum devices benefit from reproducibility and small-scale fabrication, while still being compatible with industrial techniques that enable, in principle, cheap and high volume fabrication in a highly integrated chip architecture.

In parallel, other research focused on approaches inspired by molecular electronics and single-atom devices where Coulomb blockade and spin-phenomena were investigated^84,85 (see ‘Transport through dopants’).

So far, the mentioned experiments were largely a proof of concept, and they studied physics of transport through various SETs. In more advanced and recent works, SETs were often used as the sensing element in experiments on other systems. A notable example is the work on a scanning probe microscope with an SET in the cantilever to resolve charge and capacitance changes on a sample. ⁸⁶

In 1997, Berman et al. ⁵⁴ showed how an SET with an island length of can be used for charge sensing of a GaAs-based quantum dot in close proximity to the SET. They measured the conductance through the SET with a lock-in amplifier and estimated a charge sensitivity around at . While this experiment was certainly very precise, the estimation of the sensitivity requires, for example, the capacitance from the SET island to its gate such that one should be careful with this sensitivity figure.

Another type of device for charge sensing applications is the radio-frequency single-electron transistor (RF-SET). ⁸⁷ In this device, the SET is implemented in a resonant circuit depicted in Fig. 10 that oscillates with radio frequency and is damped depending on the conductivity in the SET. Using radio frequencies, the influence of 1/f-noise becomes negligible, and the sensitivity can get close to the limit that is determined by shot-noise. ⁹ In experiments by Schoelkopf et al. in Al-SETs at , the charge change in the gate could be picked up with a sensitivity of at . RF-reflectometry, similar to this work by Schoelkopf in 1998, is still a frequently applied technique of measurement in all kinds of materials, including GaAs ⁸⁸ and silicon. ⁸⁹

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Schematic of the RF-SET circuit used by Scheolkopf et al. ⁸⁷

Theoretical work by Devoret et al. ⁹ and Korotkov et al. ⁹⁰ showed that the charge sensing potential of RF-SETs was not pushed to the limit and sensitivities down to are theoretically possible. Since then, many efforts are made towards the fabrication of SET charge sensors using MOS technology, because this technology comes with high potential for reproducibility and with more elaborate fabrication techniques. In commercial applications that can be an advantage, for example, when the SET is integrated in a larger MOS-based circuit, and the yield of working chips becomes important. Other conceivable applications include arrays of SETs that can determine not only the presence of a charge but also its position – fast charge imaging becomes possible.

Charge sensing with silicon SETs was shown for example, by Podd et al., ⁹¹ who sensed the charge in a two-dimensional electron gas quantum dot at with a second quantum dot used as a DC-SET charge sensor and island size . For an additional charge in the quantum dot, they observed a conductance change in the sensing dot that is equivalent to the change in conductance when the sensing dot goes through 0.2 times the periodic conductance oscillation from consecutive charging events.

An RF-SET was built from a silicon quantum dot in a 2DEG by Angus et al., ⁹² who could pick up the charge change in the gate with a sensitivity of at and thus got close to shot-noise limited sensing.

In conclusion, transport through SETs is well understood and demonstrated in many material systems. In research, SETs are often used as charge sensing devices, and can be realised with sensitivities close to the limit given by shot-noise around (at cryogenic temperatures). While this sensitivity is roughly three orders of magnitude better than commercially used FET charge-sensors, SETs need to become more reproducible and, depending on the application, work at higher temperatures in order to become the dominant charge sensing technology. ⁹

Electron turnstiles and charge pumps

Electron turnstiles and charge pumps are a closely related research topic to single-electron transistors and come with very similar challenges in fabrication. In an electron pump, one or several electrostatic potentials are varied through gates with frequency f to pump a well-defined number of electrons N across a channel and create a well-defined current I=Nef. Electron turnstiles can also create a well-defined current, but require a voltage bias across the device. Rather than actively pumping charges from one side to the other, they are designed to permit N electrons to travel along the potential gradient per operating cycle. For both device types, the resulting precise current could be used in metrology to define a ‘quantum’ current standard that is only based on frequency measurement. ⁹³

To reach accurate currents, the device needs to run on high frequencies f and transfer N electrons per cycle with a low error. The target region for the metric standard is estimated above a current of and an relative error per electron below ( for current). ⁹⁴ So far, devices have not been able to reach this level, but progress has been significant, as shown in the following section.

Researchers have been developing a number of different technologies in pursuit of the metric standard, including surface acoustic waves (SAW) on a GaAs heterostructure that can be used in order to create an acoustoelectric current.^95,96 The concept is based on the acoustic wave that consists of displaced surface atoms and the resulting piezoelectric potential variation on a GaAs surface. This potential variation can trap electrons and drag them along a sample, thus creating a current. The highest pumping frequency is typically limited by the fabrication of the interdigital transducer that is used to put pressure on the surface with tightly spaced, thin fingers and pump the wave. The periodicity of these fingers as well as the size of the confined area for the wave determines the wavelength and therefore the possible pumping frequency, such that fabrication is a limiting factor. The record for high-frequency SAW-pumping was set by Ebbecke et al. at . ⁹⁷ Evidence points towards a limitation in accuracy owing to electron heating that originates in the high RF-powers required for the pumping. ⁹⁸ One of the most promising realisations of SAW pumps was built by Fletcher et al., ⁹⁹ who showed a I=ef plateau in current only below the theoretical current level at which corresponds to relative error per electron.

Other efforts went into electron pumping through a series of tunnel-coupled metal islands or a turnstile from a double quantum dot.^53,100 Keller et al. ⁵³ connected seven aluminium islands that were tunnel-coupled and individually controlled with side-gates. By lowering the electrochemical potential temporarily in one island at a time, it is possible to shift a single-electron adiabatically from one end of the island chain to the other. While the accuracy of was very close to the estimated target region, the currents were significantly too small owing to the small pumping frequencies of few MHz ( ≙ 0.8 pA).

The first turnstile in a GaAs heterostructure was demonstrated by Kouwenhoven et al. in 1991. ¹⁰ Later work focused on GaAs quantum dot pumps, where only the AC-signal is applied to one gate to let electrons tunnel onto a quantum dot (low barrier), then confine them (rising barrier) and eventually raise the dot potential above the second barrier such that electrons can escape to the other side of the dot (see Fig. 11b). This process is non-adiabatic in the sense that the quantum dot is not kept at equilibrium, and the barrier modulation needs to be optimised to prevent backtunnelling and promote tunnelling in the pumping direction. ¹⁰² Giblin et al. ¹⁰¹ , therefore, optimised a pulse shape for their GaAs quantum dot that was defined with two top-gates in a GaAs heterostructure. Additionally, non-adiabatic processes were suppressed with a perpendicular magnetic field, such that the pump operated at with a current of and a deviation from the I=ef plateau of ( relative error per electron). ¹⁰¹ A picture of this device from Giblin et al. ¹⁰¹ is shown in Fig. 11 together with a sketch of the electrostatic potential induced by the gates at different points of the pump-cycle. Later devices performed at a very similar level using seven gates for the confinement of a circular quantum dot, indicating that the performance of the pump is not too sensitive to the sample layout. ¹⁰³ The best performance in GaAs heterostructures to date was achieved in a layout that consisted of a 1D channel with perpendicular gates for the creation of the dot. The device was characterised in a very precise measurement set-up, high fields (14 T) and low temperatures (100 mK). In this environment, the device produced a current of with a deviation of ( relative error per electron) from the expected current plateau. ¹⁰⁴

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(a) SEM image of the device from Giblin et al. ¹⁰¹ made from a gated quantum dot in a GaAs 2DEG. The scale bar is 1 μm. (b) potential at different times in the cycle of the periodic signal on the entrance gate . The dots represent electrons, one of which is pumped across the dot within one cycle

The GaAs charge pumps, mentioned so far, were driven with a signal on one gate and therefore non-adiabatically. In parallel, there was also research on adiabatic pumps, where the island potential is largely unaltered, and the entrance/exit tunnel barriers are periodically modulated. Errors in this type of pump are typically caused by thermally induced tunnel processes, and become less likely for high confinement in small islands. ⁸⁰ Silicon, therefore, becomes a promising platform, because miniaturisation is far developed in the fabrication processes.

One way to reach tight confinement is through dopants or trapped states in host silicon. Charge pumping using dopant potentials as ‘transport vessels’ was demonstrated by Lansbergen et al. in 2012. ¹¹ After MHz-operation was achieved, ¹⁰⁵ Tettamanzi et al. ¹⁰⁶ managed to generate a current of at with single-charge pumping through a phosphorus donor and a deviation from the I=ef plateau of (relative error per electron ). In 2014, Yamahata et al. ¹⁰⁷ used a trapped state in a MOSFET island with and currents of . However, the accuracy of their pumped current was limited by the measurement set-up such that they can only confirm an error better than per electron.

Other research in silicon pumps used an electrostatically defined island. In 2008, Fujiwara et al. ¹² managed to reach a current of at with three electrons transferred per cycle in one device made from a silicon nanowire and a charge island length between . It was, however, not possible to reach accuracies with a relative error lower than (). In 2014, Rossi et al. ⁸⁰ built an electron pump in a silicon two-dimensional electron gas with currents of and an error per electron of corresponding to . Additionally, the geometry of the gates was chosen such that the confinement in the dot can be tuned in addition energy from , and the beneficial effect of confinement for the error of the pump was demonstrated.

The record for charge pumping in silicon was recently set by Yamahata et al. ¹⁰⁸ in a silicon nanowire with quadratic cross-section and two spaced top gates. The AC-signal is only applied to one gate, such that the operating principle is similar to the non-adiabatic GaAs pumps. Consequently, a 14 T magnetic field is applied to suppress non-adiabatic error sources. The measurements were taken at a temperature between and yield a current level at of with a deviation from the I=ef plateau of , which corresponds to a relative error per electron of .

The best results for different systems are summarised in the following table:

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Author	Current[pA]	Relative error	System
Keller et al. 53	0.8		Array of metal islands
Fletcher et al. 99	431		Surface acoustic waves on GaAs
Fujiwara et al. 12	1100		Silicon nanowire
Giblin et al. 101	150		GaAs 2DEG in field
Tettamanzi et al. 106	160		P-donor in Silicon
Yamahata et al. 107	480		Trap in MOSFET
Rossi et al. 80	80		Silicon 2DEG
Yamahata et al. 108	160		Silicon nanowire

While establishing a current standard is a major achievement in this field, the devices seem to require high fields and low temperatures. For portable applications that require a precise current source, it would therefore be beneficial to work on higher temperature pumps in SETs. Pumps in silicon nanowires with islands below could therefore be the next goal after the metric standard is established.

High-temperature operation

As mentioned earlier, tight confinement in SETs or turnstiles can lead to higher temperature operation of sensors and better accuracy of charge pumps. This section is dedicated to measurements of ultra-scaled islands, which can be fabricated using a highly optimised nanofabrication or from single dopants as described in the section ‘Length scale and performance limits of state-of-the-art nanofabrication’.

While there have been measurements on few dopant devices, the addition energies were not sufficient to effectively prevent thermal activation of transport.^106,109,110 For example, the charging energy in a single-atom transistor fabricated by STM-lithography from a single phosphorous dopant in silicon is ⁸ and therefore the same order of magnitude as thermal energy ( at ). Although, so-called, deep donors have a significantly higher ionisation energy (e.g. ionisation energy of selenium in silicon: ¹¹¹ ), there have not been reports on SETs made from these donors. This section will focus on silicon-based SETs, instead of dopants because the fabrication capabilities hold great potential for small islands and high-temperature operation.

Shin et al.^27,36 fabricated a small island starting from a FinFET geometry that was etched into undoped silicon on insulator using EBL with PMMA as an etch mask. The resulting FinFET channel with a width of and a height of was covered in a spacer layer and etched in a window using a ZEP520A mask that was patterned by EBL. The resulting height of this part of the nanowire was with a step-like increase to the level of the rest of the silicon. The following oxidation step is the key process in the fabrication! On the one hand, the size of the silicon channel can be controlled via oxidation time, because the oxidation starts from the exposed silicon surface and moves towards the centre of the channel. On the other hand the authors attribute the arising tunnel barriers to the strain introduced via PADOX over the step on the sides of the etched window. The resulting island can be controlled with a gate made from poly-silicon that is deposited in a self-aligned manner using a spacer layer (see Fig. 12). In this process, the spacer is coating the device and therefore reduces the width of the etched trench, such that the tip of the gate is only wide.

The devices show Coulomb blockade up to and excited states at lower temperatures can be explained in an atomistic model (Fig. 13).^27,36 Especially the agreement with the atomistic model is a strong evidence for a single-charge island with strong confinement.

Room-temperature operation of an SET has further been reported by Lavieville et al. ⁷² using a gate in a nanowire that was fabricated from a FinFET architecture and oxidised to reduce the silicon nanowire diameter down to . The main difference to the fabrication by Shin et al. is, that it does not rely on PADOX for the creation of barriers. Instead, the devices are doped after gate deposition, such that the gate acts as a mask and the island region initially remains undoped. Therefore, the barriers could originate in a change of doping density, but the authors do not elaborate on that. Overall, the data are not as convincing as in the work by Shin et al., where several Coulomb diamonds could be measured and the island energies agree with an atomistic model. Instead, the high-temperature curves only show one peak that persists from low temperature to (Fig. 14).

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12

Devices from Shin et al.^27,36 (a) SEM Top-view. (b) 3D schematic and TEM cross section of the channel. (c) schematic cross section of the device with a tetraethyl-orthosilicate (TEOS) spacing layer. (d) TEM of the device cross-section

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13

(a) Current as a function of gate-voltage at different temperatures from the device by Shin et al. (b)–(d) Current as a function of gate-voltage and bias-voltage at different temperatures^27,36

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14

Conductance G as a function of gate-voltage for different temperatures in the devices from Lavieville et al. ¹¹² Inset: Transmission electron microscope picture of the wire cross section

One reason for the small amount of reports on room-temperature operation in lithographically fabricated devices could be a lack of reproducibility. Poor reproducibility can also be related to uncertainties, such as to whether the island is created in the intended way or with a random, unknown process.

Improved reproducible techniques for the fabrication of channels and gates are the subject of current work.^34,74 In the future, it might therefore be possible to build ultra-scaled devices in mass fabrication on a silicon basis for room-temperature operational SETs or high accuracy single-electron pumping.

Dopants in silicon: Spectrum, location and dielectric effects

As early as 1955, Kohn et al. ¹¹⁴ calculated the spectrum of P, As and Sb dopants in bulk silicon, although at that point few dopant devices were far from realizable. Almost three decades later metal-insulator transitions were a very applied research field. A theoretical study of metal-insulator transitions of arsenic-doped silicon by Newman et al. ¹¹⁵ revealed that the critical doping was higher than expected from a simple estimation using Bohr radii. Diarra et al. ⁶⁷ investigated the ionisation energies of dopants in nanowires theoretically. The results show that for devices at the length scale of ionisation energies are significantly dependent on surrounding dielectrics, and therefore differ substantially from the bulk values. As mentioned earlier, the experimental observation of this dopant deactivation effect was reported by Björk et al. ⁶⁶ and represents an important issue in semiconductor industry.

The first experiments on few dopants included the measurement of single-dopant transport in GaAs devices, such as the work by Geim et al. ¹⁰⁹ In 1994, they measured the interaction of two closely spaced silicon dopants by means of electrical transport as a function of bias-voltage across the device. They find a dopant pair that forms a ‘dopant molecule’, and model the ionisation energy of such a system as a function of dopant spacing to identify a possible mechanism that explains conductance features in pinched-off transistors. Further work by Savchenko et al. ¹¹⁶ and Kuznetsov et al. ¹¹⁷ focuses on the current as a function of gate-voltage through dopants in a GaAs transistor, which, among other things, shows some of the features that were predicted by Geim et al. These early experiments proved that transport through few dopants can be studied and be used to investigate important properties of dopants in small-scale devices, for example, ionisation energies.

In the following years, electrical transport through dopants in silicon devices was the focus of many efforts. Before some important experimental work was done, Friesen ¹¹⁸ could calculate the spectrum of a phosphorous donor in an electric field more precisely. In 2006, Sellier et al. ¹¹⁹ reported a detailed spectroscopy of two donors in a gated silicon FinFET. By tuning the gate-voltage, they observed transport through two arsenic donors in the ionised As⁻ and neutral As⁰ state. They measured the binding energy of the first valence electron () for the first (second) arsenic donor and attribute the difference between donors to fluctuations in local potential owing to, for example, surface effects.

More recent work focused on transport through two coupled arsenic donors in a SiFET channel with respect to ionisation energies and coupling. ¹¹ Apart from electron pumping through the donors the authors show how they can tune the ionisation energy with a top gate from . Other efforts included p-doped devices like Si:B ¹²⁰ or work on more exotic dopants, for example, temperature migrated Pt in a MOSFET Schottky barrier. ¹¹⁰

In conclusion, the measurements on few dopant devices are valuable for industrial processes, because they investigate how dopants behave in future small-scale devices. Additionally, they represent the first step towards single-atom-based devices.

Towards single-dopant devices and deterministic dopant positioning

After investigating the effect of the environment of a dopant in much of the work described in the last section, research focused on the determination of the position of a dopant in the device. This included experiments by Lansbergen et al., ¹²¹ who studied the hybridisation of arsenic donor states with surface states at a silicon oxide interface with respect to the electron wavefunction and energy spectrum. Among other things, they characterised the transition from a surface state (interfacial confinement regime), over a hybridised state to a bulk state (Coulomb confinement regime) as a function of dopant location. Pierre et al. ³ focused on the association of dopant location to ionisation energies. They observed substantial shifts in ionisation energies for donors in a small CMOS channel, and attribute it to close proximity of the oxide. Although the statistical argument in their analysis does not eliminate possible pairs of donors in the channel and therefore the uncertainty in the measured ionisation energies is high, they illustrate qualitatively how dopants can add to OFF currents of a transistor at room-temperature and how location of dopants can matter. Khalafalla et al. ¹²² investigated how the lateral position of a boron dopant can be determined with respect to the leads in an FET channel using a series of low-frequency transport measurements.

A different way of determining dopant positions was demonstrated by Verduijn et al. ¹²³ by means of radio-frequency reflectometry. This technique is based on capacitive coupling rather than current measurement. Since capacitive coupling is a function of distance, the lateral position of the dopant can be extracted without the need for high precision current measurements in case of low tunnel coupling. A further advantage of this technique is that overall transport through the channel is not needed to create a measurable signal. Tunnelling of charges between individual dopants can thus be registered.

In conclusion, the position of a dopant can be inferred to some extent from its interaction with the environment or other basic properties like activation energy. Furthermore, reflectometry enables new types of experiments on tunneling events within a device.

The big downside of all presented devices in this section is their reproducibility, because dopant placement is a stochastical process such that it is not trivial to get arrays of reproducible samples. As mentioned before, there is another way to fabricate single or few dopant devices using a scanning tunnelling microscope: hydrogen-STM lithography. Fuechsele et al. ⁸ demonstrated transport through a single-atom transistor fabricated with this technique. An STM picture of this device is shown in Fig. 15 together with the conductance through the device as a function of bias and gate-voltage. From the size of the Coulomb blockade region in the data, they can measure the addition energy of the phosphorous dopant to be . Later work by the same group involved a double quantum dot ¹²⁴ and a triple quantum dot ¹²⁵ made from phosphorous dopants.

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15

(a) STM image of the single-atom transistor showing the phosphorous dopant, Source (S) and Drain (D). (b) Conductivity as a function of bias-voltage and gate-voltage showing Coulomb blockade regions corresponding to three different charge states P, P⁻ and P⁰. The extracted charging energy of the dopant is ⁸

Future issues

Transport is well understood through many types of conventional dopants, but some future devices may require higher charging energies and therefore different dopants. The required deep dopants will come with new challenges for measurement and device fabrication. RF-reflectrometry might be a more suitable measurement technique than DC-transport, because it does not require charges to move all the way through a device and dopants do not need to be tunnel-coupled to both leads. This creates the flexibility for dopant positioning that is highly needed for dopants with small Bohr-radii.

Apart from transistor-type devices, single dopants in silicon were also used for experiments in the field of quantum information processing. ¹⁷ In fact many of the presented results and techniques in this section were developed in pursuit of spin qubits and ultimately the proposal for a dopant-based quantum computer by Kane.^13,113 In the future, it is therefore likely that transport experiments are mostly used as a method of read-out for qubits, and a big fraction of future research in the field will be working towards quantum information processing applications.