A laboratory exercise to improve student understanding of dominant pole analysis and high-frequency modeling of Field Effect Transistors

Abstract

In the quest for increased student understanding of the principles underlying high-frequency response of Field Effect Transistor amplifiers, a laboratory exercise employing a unique method to determine the intrinsic transistor model capacitances was used. The method employs two simple measurements: determination of the high 3-dB frequency for a common-source amplifier being driven by a Thévenin source with two different output resistance values. Circuit simulation results utilizing these experimentally determined intrinsic capacitances show much greater correlation to experimental results than those typically obtained using manufacturer-supplied values. Students participating in the laboratory exercise reported good gains in knowledge levels and reasonable gains in confidence levels.

Keywords

Assessment amplifier frequency response transistor modeling Miller's Theorem laboratory

Introduction

Electrical engineering programs strive to closely link hand calculations, computer simulation, and experimental results in the analysis and design of transistor amplifiers. This linkage is typically accomplished in laboratory portions of electronics courses using well-known conversions between manufacturer-supplied data, either from data sheets or SPICE parameters, and hand calculation parameters.¹ Low-frequency models can be improved over manufacturer-supplied data through the use of a transistor curve tracer to determine model parameters for individual transistors. Using such modified models leads to good correlations in amplifier quiescent conditions and low-frequency performance.

At high frequencies, however, determination of model parameters is problematic. In the case of both Bipolar Junction Transistors (BJTs) and Field Effect Transistors (FETs), high-frequency performance is modeled by capacitors connected between nodes of the transistor model. Several methods have been proposed for measuring these capacitance parameters.^2,3 Unfortunately, some methods propose etching materials from a semiconductor structure and are not practical in a typical instructional electronics laboratory setting.

In addition, the typical breadboard used in instructional laboratories may introduce significant stray capacitance in the circuit, increasing the variation between experimental results and those obtained by analytic or simulation techniques. In general, this variation can be detrimental to student confidence and learning. Students often seem to feel that either the models failed or that the parameters supplied by manufacturers are overly optimistic.

A simple laboratory exercise that would allow students to determine transistor model capacitance parameters experimentally was explored. In order to verify the model, analytic, simulation, and experimental results are compared. The course instructors assessed whether this exercise increased student knowledge concerning high-frequency modeling of transistors and their confidence in using those models to predict amplifier performance.

Theoretical background

The hybrid-π, small-signal, high-frequency model of a FET is shown in Figure 1. The high-frequency behavior of the FET is modeled though the two capacitors, C_gs and C_gd. Good approximations of those intrinsic FET capacitor values must be obtained in order to have accurate modeling of transistor high-frequency performance. While the technique used is applicable to both BJTs and FETs, it was decided to use a JFET for this first effort. The decision was based primarily on the well-known JFET transformations of model capacitors to SPICE parameters.¹ A depletion MOSFET would be another good choice: the transformations for enhancement MOSFETs are more complicated and BJTs suffer the dilemma of converting the two model capacitors into the three SPICE parameters used to describe high-frequency effects.

When a FET is placed into a simple common-source amplifier, the high-frequency response is described by two poles. In nearly all common-source amplifiers, one of these poles is dominant and the high 3-dB frequency is essentially the lower of the two pole frequencies. Table 1 is a summary of the common-source pole frequency equations as derived from a simple application of Miller's Theorem and found, in various formats, in most electronics textbooks.^4,5 It is important to note that some electronics textbooks list only the Miller effect pole (ω_HA)^6,7 and as a result have predetermined that the Miller effect pole is always the dominant pole, while others determine both but specifically state that the Miller effect pole is dominant.⁸ As shown in this article and in the literature,⁹ the Miller effect pole is not always the dominant pole.

Table 1.

Summary of Field Effect Transistor (FET) common-source pole frequencies.

Pole	Pole frequencies
A	$ω_{HA} = \frac{1}{{C_{gs} + (1 + g_{m} [r_{d} / / R_{D}]) C_{gd}} R_{i}}$
B	$ω_{HB} = \frac{1}{{1 / 1 g_{m} g_{m} + [r_{d} / / R_{D}]} C_{gd}}$

Of particular significance to the development of the laboratory exercise is that pole A (as described by ω_HA) is highly dependent on the signal source output resistance, R_i (the parallel combination of biasing resistors and the signal source output resistance in the circuits of Figure 2), while pole B (as described by ω_HB) is independent of the signal source output resistance. That dependence-independence relationship of the poles is such that pole A is dominant when the signal source output resistance is sufficiently large and pole B is dominant when the signal source output resistance is sufficiently small.

The experiment described in this article, developed by Kim and Schubert,¹⁰ takes advantage of the switching of dominant poles with signal source output resistance in order to easily calculate the transistor model capacitors, C_gs and C_gd. The high 3-dB frequency of a single amplifier driven by two different signal sources is measured: once with a low output resistance (typically the 50 Ω output resistance of a function generator) and once with a resistor inserted between the signal source and the amplifier. Kim and Schubert then directly compute C_gd from the high 3-dB frequency for the low output resistance case and, using that value of C_gd, they compute C_gs from the high 3-dB frequency for the high-output resistance case. After the intrinsic capacitor values are calculated from the measured dominant pole test circuits using simple dominant pole analysis, SPICE models are back-calculated using the standard expressions for converting small-signal model capacitors to the capacitance parameters used in the SPICE models.

The laboratory exercise

The students participating in this laboratory exercise were typically in their second semester of a two-semester, junior-level electronics course. In the first semester, they became familiar with low-frequency analysis, modeling, simulation, and experimental testing of both BJT and FET amplifiers. Prior to this laboratory exercise, the students had received instruction and homework exercises in high-frequency performance of single-transistor BJT and FET amplifiers. The instruction included the derivation of high-frequency amplifier pole frequencies.

In the laboratory, the students were given a 2N5486 JFET (arbitrarily chosen) and asked to determine the DC characteristic parameters of that transistor (I_DSS, V_PO, and V_A) using a transistor curve tracer and appropriate calculations. The students had performed these measurements several times previously in other laboratory exercises, so a MathCAD template was provided to assist in the calculations and save time.

Students were directed to build the circuit of Figure 2(a) and determine its high 3-dB frequency using realistic values for the coupling and bypass capacitors. A previous experiment had explored the effect of coupling and bypass capacitors on the low 3-dB frequency and students were expected to use that information in choosing appropriate capacitor values. The circuit was then altered to become Figure 2(b) by reducing the source output resistance: R1 in Figure 2(a) (1 kΩ) was changed to become R11 in Figure 2(b) (50 Ω) – no other changes to the circuit were made.

Students were reminded that it is important that the poles be dominant poles: the signal source output resistance values must be chosen so that the high 3-dB frequencies for the two circuits differ by at least a factor of four. From the results of these two experiments, students determined the JFET model capacitance parameters C_gs and C_gd for the JFET as biased in these two circuits. Again, a MathCAD template was provided to assist in the calculations and save time. From the values obtained above and the bias conditions for the FET, the SPICE parameters CGD and CGS were calculated under the typical SPICE-parameter assumption that PB = 0.6 and M = 0.5.

Finally students were asked to build the circuit of Figure 3 (again, using realistic values for the bypass and coupling capacitors). While this circuit is a similar common-source amplifier, the quiescent conditions for the JFET, as well as the various resistor values, are somewhat different. Students were to compare experimental DC and AC performance to Multisim™ (the SPICE-based simulator available to the students) simulations which used:

the Multisim™ model for the 2N5486 (unaltered);

the Multisim™ virtual model modified to reflect the JFET parameters determined in this experiment.

Comments on the differences/similarities in the results were recorded. In order to cancel out any oscilloscope probe frequency effects, students used the same type of probe for both input and output measurements.

Experimental observations

Using a Tektronix 571 transistor curve tracer, students determined values for I_DSS and V_po by choosing two pairs of I_D and V_GS at a constant value of V_DS. Similarly, the early voltage, V_A, was determined from two pairs of I_D and V_DS values at a constant value of V_GS. A comparison of student results and manufacturer's SPICE parameters is presented in Table 2. As expected, student results for the low-frequency parameters showed good correlation with the manufacturer's typical data (listed in the “Multisim” column) for VTO and BETA. The parameter LAMBDA only has significant impact on circuits with large impedances connected to the drain or source terminals: the somewhat larger variation in values is not significant for this experiment. The SPICE column parameters were derived from the student data using well-known relationships.¹

Table 2.

DC JFET parameters.

Parameter	Average student value	Derived SPICE value	Multisim	Average variation
V_po (VTO)	−3.57	−3.57	−3.847	−7.2%
I_DSS (BETA)	11.4mA	0.900 × 10⁻³	0.83266 × 10⁻³	+8.0%
V_A (LAMBDA)	73.0 V	13.7 × 10⁻³	19.1513 × 10⁻³	−28.5%

From the quiescent conditions of the circuits of Figure 2 (both circuits have the same quiescent conditions and consequently the same JFET model parameters), students determined the necessary transistor small-signal parameters using standard relationships.¹

The student experimental high 3-dB frequencies for the two source output resistance cases were quite consistent (a standard deviation of about 1/20 of a decade in each case)

f_{H (50 Ω)} = 704 kHz and f_{H (1 Ω)} = 132.5 kHz

(1)

However, Multisim™ SPICE simulation using the manufacturer-supplied capacitance values for the 2N5486 JFET produces high 3-dB frequencies of 98.96 MHz and 21.0 MHz for the low and high output resistance cases. These values are about 2.2 decades higher than the student experimental results. Such large discrepancies between simulation and experiment are troubling for students.

Students then calculated the two intrinsic JFET model capacitor values using their experimental high 3-dB frequencies determined from each of the two circuits of Figure 2

C_{gd} = \frac{1}{{1 / 1 g_{m} g_{m} + [r_{d} / / R_{D}]} 2 π f_{H (50 Ω)}}

(2)

and

C_{gs} = \frac{1}{1 k Ω \times 2 π f_{H (1 k Ω)}} - (1 + g_{m} [r_{d} / / R_{D}]) C_{gd}

(3)

From those JFET model capacitor values, the SPICE model parameters were then calculated using the bias conditions and standard transformations¹

CGD = C_{gd} (1 + \frac{| V_{GD} |}{PB}) M and CGS = C_{gs} (1 + \frac{| V_{GS} |}{PB}) M

(4)

where typical values of the gate p-n potential and the junction grading coefficient, PB = 0.6 and M = 0.5, respectively, were used.

If the above-stated average student values are used, the intrinsic capacitor values are C_gd = 108.6 pF and C_gs = 531.1 pF. These values can be converted to the SPICE parameters CGD = 483.6pF and CGS = 1.117nF. Placing these values into Multisim™ for the two circuits results in high 3-dB frequencies of f_H(50 Ω) = 718 kHz and f_H(1kΩ) = 124 kHz. Each of these values is within 1/30 of a decade of the experimental value and shows good correlation between practice and the model.

The students then connected the test JFET circuit of Figure 3 and determined the high 3-dB frequency. As shown in Table 3, simulation using manufacturer's supplied JFET parameters predicted a high 3-dB frequency 1.9 decades higher than the experimental results. Student-determined SPICE parameters gave much better results: typically within 0.2 decades of the experimental results. Given the variability of experimental technique, these results show excellent correlation with the new model.

Table 3.

Comparison of simulation predictions and average experimental results.

Parameter	Average student experimental value	Simulation: student values	Simulation: manufacturer's values
I_D	2.5 mA	2.43 mA	2.66 mA
V_DS	7.95 V	8.10 V	7.55 V
High 3-dB	535 kHz	336 kHz	46.8 MHz

From the instructor viewpoint, the experiment went smoothly with a few areas for improvement. Some students misunderstood the instruction to use “realistic values for the coupling and bypass capacitors” when building their test circuits. The instructions have been modified to ensure that the capacitor bypassing the resistor connected to the FET source terminal is sufficiently large so that it effectively shorts that resistor at frequencies well below the high 3-dB frequency. Modeling the high-frequency performance of the transistor is sensitive to accurate measurements of the high 3-dB frequency. It is vital that the function generator used is capable of high-quality sine waves at the high 3-dB frequencies measured, and that students make sure that the input signal is of appropriate magnitude so that the transistor amplifier is operating in its linear region. Linearity can be easily determined with an “x–y” plot on the oscilloscope of the input–output relationship at midband frequencies.

It should also be noted that the two necessary signal source resistance values used in this experiment can vary with transistor and circuit element values. When designing this experiment using different transistors or circuit elements, the resistance values chosen should be alternately larger and smaller than the dominant-pole crossover resistance value (the value where ω_HA = ω_HB)

R_{i (crossover)} = \frac{{1 / g_{m} + [r_{d} / / R_{D}]} C_{gd}}{{C_{gs} + (1 + g_{m} [r_{d} / / R_{D}]) C_{gd}}}

(5)

A simple voltage divider can be used, if necessary, to lower the apparent output resistance of the signal source (typically 50 Ω).

Assessment of student knowledge and confidence

One of the aims of this study was to assess student learning in the laboratory concerning frequency response and simulation of transistor circuits. Specifically:

Does this methodology increase basic understanding of transistor amplifier and design tools?

Does student confidence in applying the concepts learned increase?

Short questionnaires were designed to provide insight into the student level of knowledge concerning amplifier circuits and their confidence in applying that material. Just prior to beginning the laboratory exercise, students were asked to score (on a scale from 1 to 5) their prior knowledge. To provide further insight into actual student knowledge level, students were asked to respond with a short answer to the knowledge queries. After the exercise was completed, the questionnaires were again completed by the students and the post-exercise written responses scored by the investigators to measure changes in knowledge level. In order to track individual student incremental changes, students submitted the surveys together at the end of the exercise. All surveys were submitted without any identifying markers so that student anonymity would be preserved. The use of student-assigned scores to assess gains in student knowledge and confidence has been successfully used by the investigator team in previous studies.^11,12

The following seven queries concerning knowledge concerning transistor capacitance modeling were asked before and after the laboratory exercise.

What are the capacitors used in the high-frequency small-signal model of Bipolar Junction Transistors (BJTs)?

What are the capacitors used in the high-frequency small-signal model of Field Effect Transistors (FETs)?

How do you determine the small-signal model capacitors for a particular transistor?

How is Miller's Theorem used (in words) for transistor amplifier high-frequency small-signal models?

What is a dominant pole (high frequency)?

What are the primary factors affecting a dominant pole?

In a transistor amplifier, what are some of the major factors contributing to mismatches between analytic and computer simulation results?

The knowledge score was based on the following scale.

1 = No clue, this concept is new to me.

2 = Low, I have only heard about the concept.

3 = Moderate, I know about the concept, but have not applied it.

4 = High, I know the concept and have tried it.

5 = Superb, I know the concept and have successfully applied it.

Students performing the exercise in the spring 2013 semester reported initial knowledge at low level (mean = 2.35) and reporting changes in mean scores due to the laboratory exercise to 3.01 (moderate knowledge) as reported in Table 4. Overall students reported a gain in knowledge in 47% of their responses to these seven knowledge-based queries. The mean knowledge level increased for four of the queries (1, 2, 5, and 6) by essentially a full level (0.93 to 1.11 levels) with over half of the students reporting an increase in knowledge in each case. All students indicated a positive increment on some questions.

Table 4.

Knowledge survey response distribution.

Response distribution in %	Pre/post	No clue	Low	Moderate	High	Superb	Mean	Standard deviation
1. What are the capacitors used in the high-frequency small-signal model of a BJT?	Pre	26	21	42	11		2.37	0.98
	Post	5	18	36	23	1	3.32	1.10
2. What are the capacitors used in the high-frequency small-signal model of an FET?	Pre	32	26	42			2.11	0.85
	Post	4	22	43	22	9	3.09	0.97
3. How do you determine the small-signal model capacitors for a particular transistor?	Pre	26	32	32	11		2.26	0.96
	Post	13	26	43	9	9	2.74	1.07
4. How is Miller's Theorem used for transistor amplifier high-frequency small-signal models?	Pre	11	21	37	26	5	2.95	1.05
	Post	9	26	22	43		3.00	1.02
5. What is a dominant pole (high frequency)?	Pre	53	11	32	5		1.89	1.02
5. What is a dominant pole (high frequency)?	Post	9	17	57	17		2.83	0.82
6. What are the primary factors affecting a dominant pole?	Pre	42	32	21	5		1.89	0.91
6. What are the primary factors affecting a dominant pole?	Post	5	9	68	18		3.00	0.67
7. In a transistor amplifier, what are major factors for mismatches between analytic and simulation results?	Pre	16	5	53	21	5	2.95	1.05
	Post	17	4	35	35	9	3.13	1.19

BJT: Bipolar Junction Transistors; FET: Field Effect Transistors.

Student responses to queries 3, 4, and 7 showed smaller average gains in reported knowledge. Query 3 (determination of capacitance values) showed an average gain of 0.47 levels with 47.4% of the students reporting an increase in knowledge. Queries 4 (use of Miller's theorem) and 7 (sources of mismatch) reported average gains of 0.06 and 0.11 levels, respectively, with 21.1% and 36.8% of the students reporting gains, respectively.

Another portion of the questionnaire was designed to assess student confidence in applying this methodology. The following nine queries were asked before and after the exercise was performed in order to assess student confidence.

I can design transistor amplifier circuits.

I can apply Miller's Theorem to create small signal models of electronic circuits.

I can perform high-frequency small-signal analysis of analog electronic circuits

I can determine circuit high-frequency dominant poles.

I can use computer simulation tools for analyzing electronic circuits.

I can use a circuit simulation tool to alter transistor model parameters.

I can convert between the transistor parameters used in analytic models and those used in circuit simulation models.

I can compare high-frequency cut-off calculations for transistor amplifiers circuits and verify performance characteristics using computer simulation.

I can reconcile mismatches between analytic and simulation high-frequency cut-off results.

The confidence score was based on the following scale.

1 = No clue, I have no idea if I can apply the concept.

2 = Low, I have heard of the concept, but have little confidence that I can apply it.

3 = Moderate, I think I understand the concept, but am unsure about applying it.

4 = High, I am fairly sure I understand the concept and am fairly sure I can apply it.

5 = Superb, I am very confident that I understand the concept and can apply it to a new problem.

This same group of students started with a moderately high overall level of confidence (mean value of 3.67) and experienced a moderate overall increase (0.2 levels). Overall, 21.6% of the student responses showed an increase in confidence level. All students indicated a positive increment on some questions. The detailed distribution of students' answers before and after the exercise is shown in Table 5.

Table 5.

Confidence survey response distribution.

Response distribution in %	Pre/ post	No clue	Low	Moderate	High	Superb	Mean	Standard deviation
1. I can design transistor amplifier circuits.	Pre		9	14	50	27	3.95	0.88
1. I can design transistor amplifier circuits.	Post		4	13	58	25	4.04	0.73
2. I can apply Miller's Theorem to create small-signal models of electronic circuits.	Pre		18	50	27	5	3.18	0.78
	Post		17	33	33	17	3.50	0.96
3. I can perform high-frequency small-signal analysis of analog electronic circuits.	Pre		23	32	36	9	3.32	0.92
	Post		13	21	42	25	3.79	0.96
4. I can determine circuit high-frequency dominant poles.	Pre		9	18	55	18	3.82	0.83
4. I can determine circuit high-frequency dominant poles.	Post		4	21	58	17	3.88	0.73
5. I can use computer simulation tools for analyzing electronic circuits.	Pre		5	18	41	36	4.09	0.85
	Post		4	6	50	44	4.17	0.80
6. I can use a circuit simulation tool to alter transistor model parameters.	Pre		7	21	29	43	4.07	0.96
	Post			6	50	44	4.38	0.60
7. I can convert between the transistor parameters used in analytic and circuit simulation models.	Pre		9	45	18	27	3.64	0.98
	Post		8	42	21	29	3.71	0.98
8. I can compare high-frequency 3-dB cut-off calculations verify performance using simulation.	Pre		9	50	23	18	3.50	0.89
	Post		13	33	29	25	3.67	0.99
9. I can reconcile mismatches between analytic and simulation high-frequency cut-off results.	Pre	5	5	41	23	27	3.64	1.07
	Post	4	4	38	25	29	3.71	10.6

Three of the confidence queries (2, 3, and 6) experienced gains in student confidence greater than 0.3 levels and four of the queries (2, 3, 6, and 7) had more than 27% of the students reporting increases in their confidence.

Summary

The development of a meaningful student laboratory experience in transistor amplifier frequency response with a closed loop approach for finding intrinsic transistor capacitor values using SPICE and circuit analysis met its goals. Good correspondence between simulation results and model parameter calculations were achieved. In addition, students reported good increases in knowledge concerning the subjects covered and positive increases in confidence in applying the methodology covered.

Footnotes

Acknowledgement

USD Institutional Review Board approval for this project was obtained for the 2012–2013 academic year.

Conflict of interest

None declared.

Funding

This research received no specific grant from any funding agency in the public, commercial, or not-for-profit sectors.

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