Unique fractional calculus engineering laboratory for learning and research

Abstract

In this paper, a novel prototype laboratory is presented for engineering education, in which experiments are based on the fractional calculus. The prototypes of analog and digital fractional-order proportional-integral-derivative (PID) controllers are built in the laboratory. These fractional-order PID controllers are applied to linear and nonlinear plants to demonstrate the effectiveness of fractional-order calculus in real time. These experiments are designed, developed, and implemented on the analog and digital platforms. These controllers are integrated to control the DC motor, brushless DC motor, and magnetic levitation modules through hardware-in-loop as well as stand-alone systems. The analog type of fractional-order PID implementation is carried out by using passive components (i.e. resistances and capacitances) with an operational amplifier. However, real-time digital implementation is carried out using field-programmable gate array and digital signal processor. This paper describes how the experiments on fractional calculus can be tailored for graduate, undergraduate students’ education and extended for research in this emerging area.

Keywords

Controller electrical engineering field-programmable gate array fractional calculus laboratory simulation

Introduction

The concept of fractional calculus and fractional-order circuits is emerging slowly in the engineering domain.¹ Fractional calculus acts as a generalization to the classical calculus.² It shows many beneficial applications in several fields. It includes control systems, industrial drives, magnetic levitation (MagLev), inverted pendulum, electric motors, robotics, and biomedical applications as presented in the literature.^3–14 These concepts are somewhat new to circuit theory and have exhibited applications in fractional-order hold circuit,⁴ power electronics,¹⁵ integrator and differentiator circuits,^16,17 and filters^18,19 with potentially many other engineering applications. Chen et al.²⁰ offered a modeling and analysis method for the fractional-order DC–DC converters. Dimeas et al.²¹ implemented fractional-order controller in analog form for a DC motor. Debnath²² has precisely reviewed the applications of fractional calculus in diverse domain of engineering and science. Fractional-order models of supercapacitors, batteries, and fuel cells have been surveyed in Freeborn et al.²³

Fractional differential equations characterize the fractional systems.⁶ In order to solve the fractional differential equations, a combination of Laplace transform and fractional calculus methods can be used.³ It is a known fact that the fractional systems involve infinite memory; however, the integer-order systems are local and point property.⁵ It is significant to express the fractional-order system using a finite difference equation. For that, integer-order approximations are mainly used in continuous-time domain.^3–6 Some methods are available that can be used to compute the integer-order approximation of fractional operator.^3,24–28 The approach to realize analog fractional systems is available in the literature.^25–27 Adhikary et al.²⁹ reviewed some significant research work, along with their success and limitations, in the field of fractional circuit realization.

The design of digital fractional system includes the discretization of fractional-order operators.²⁸ Direct discretization and indirect discretization are the two generally practiced methods. Generally, the ideal frequency response is approximated using either an infinite-length impulse response (IIR) filter or a finite-length impulse response (FIR) filter.³ FIR filters are often selected due to their effective implementation aspects. As compared to IIR filters, FIR filters have no constraint on maximum sampling rate and they are always stable.³⁰ Experimentation plays an important role in learning and research.³¹ Fractional systems can be implemented using a microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), etc. Jiang et al.³² proposed that the FPGA is an effective platform to realize high throughput, high quality approximations of fractional systems. In Muresan et al.,³³ an FPGA-based fractional controller is developed for a class of DC motors. The major objectives of this paper include:

A common algorithm of constant phase shaping is proposed to select the pole-zero (p-z) pairs for analog and digital implementation.

Analog fractional integrator circuits are implemented using commercially available passive components.

The analog fractional-order PID (FO-PID) controller is tested with DC motor emulator as a plant.

Digital fractional integrator is implemented on FPGA.

The digital FO-PID controllers are applied to DC motor, brushless DC (BLDC) motor, and MagLev system.

To address the all above objectives, the “Fractional Calculus Engineering Laboratory” is developed at Visvesvaraya National Institute of Technology, Nagpur, India. This work is organized as follows: the preliminaries of a fractional calculus are given in the following section. The laboratory experiments are discussed in “Examples of laboratory experiment” section. The paper is concluded in “Conclusion” section with the summary of lab outcomes.

Preliminaries

Fractional calculus investigates the feasibility of using the real/complex number powers of the integration operator. The basics of fractional calculus are available in the literature.^3–6 The real-order operator is inferred as follows in equation (1)

D^{α} = {\begin{matrix} \frac{d^{α}}{d t} & α > 0 \\ 1 & α = 0 \\ \int_{a}^{t} {(d τ)}^{- α} & α < 0 \end{matrix}}

(1)

Riemann–Liouville definition of fractional operator is shown in equation (2)

_{a} D_{t}^{α} f (t) = \frac{1}{Γ (n - α)} {(\frac{d}{d t})}^{n} \int_{a}^{t} \frac{f (τ)}{{(t - τ)}^{α - n + 1}} d τ

(2)

where

(n - 1) \leq α < n, α

is the real number,

n

is the integer, and

Γ (.)

is the Euler’s gamma function. The Laplace transform of equation (2), under zero initial conditions, is shown in equation (3)

L {_{a} D_{t}^{\pm α} f (t)} = s^{\pm α} F (s)

(3)

s^{\pm α}

needs to be approximated in integer order. There are various approximation methods available.^3–6 But, the method proposed in Dhabale et al.²⁵ is at par with any other methods.

Method of approximation

Every transfer function can be represented by its pole-zero pairs.^3–6 The Bode’s phase plot of fractional transfer function is constant at $\pm α 90^{°}$ and Bode’s magnitude plot has a slope of ± α 20 dB/dec. This can be acquired by interlacing of p–z pairs alternately on negative real axis. Thus, the nth order approximation is achieved within the desired frequency band (ω_L, ω_H) which depends on band of error $(ε)$ around desired phase angle $ϕ_{r e q} = α 90^{°}$ .^25,26 The proposed algorithm which maintains the phase value within the tolerance of about $1^{°}$ is developed to get the p–z pairs. The flowchart of a proposed approximation method is shown in Figure 1. The same algorithm can be used for analog and digital realization. The rational approximation obtained with this algorithm is fairly good for the practical implementation. The poles and zeros are obtained as follows in equation (4)

\begin{array}{l} P o l e_{1} = 10^{[\frac{ϕ_{r e q} + 45 l o g ω_{L}}{45} + 1]}; Z e r o_{1} = 10 ω_{L}; \\ P o l e_{2} = 10^{[l o g (P o l e_{1}) + 2 - μ]}; Z e r o_{2} = 10^{[l o g (Z e r o_{1}) + 2 - μ]} \\ t i l l P o l e_{n} \geq ω_{H} \end{array}

(4)

The basic steps of the algorithm are as follows:

Step I: Consider the values of α and the desired frequency band (ω_L, ω_H).

Step II: Calculate the pole-zero pairs using equation (4).

Step III: Plot asymptotic and exact Bode plot. Check the average value of phase angle. If the average value of the angle over the desired frequency band is in required tolerance band then go for either analog or digital implementation.

Step IV: For analog implementation, find out the values of resistances and capacitances.

Step V: For digital implementation, convert the continuous time transfer function into discrete time transfer function using “Tustin” as discretization method and choosing sample time.

Examples of laboratory experiment

Various experiments are designed based on the fractional calculus and presented next.

Lab 1. Design of analog fractional integrator

The aim of the experiment is to realize the fractional integrator using analog components. The algorithm, as shown in Figure 1, gives p–z pairs for α = −0.2, −0.5, and −0.8 as listed in Table 1. The corresponding phase plot, with frequency band ω_L = 100 rad/s and ω_H = 10000 rad/s, is presented in Figure 2. The rationally approximated transfer function is realized by the cascading of basic two-port networks, where one-port network is having first-order impedance function with a zero. Partial fraction expansion of Z_new gives $Z_{n e w} (s) = \frac{s + z}{s + p} = k' + \frac{k}{s + p}$ . This can be presented with resistance $R_{f}'$ in series with $R_{f} - C_{i}$ parallel as shown in Figure 3 and impedance function of $Z_{n e w} (s) = R_{f}' + [(s + \frac{1}{R_{p} C_{i}}) / (s + \frac{1}{R_{f} C_{i}})]$ where $R_{p} = \frac{R_{f} R_{f}'}{R_{f} + R_{f}'}$ . For fractional-order integrator, the zero is greater than the pole as referred in Table 1. For the realization of ith two-port network portion, available capacitor (C_i) value is selected and then resistance values are computed as: $R_{f} = \frac{1}{p_{i} C_{i}}, R'_{f} = \frac{1}{(z_{i} - p_{i}) C_{i}}$ . The p–z values in Table 1 and the above formulas are used to get component values as listed in Table 2. Total six pole-zero pairs are required to obtain the analog implementation of fractional integrator of order 0.5. Hence, six number of two port networks (as shown in Figure 4) are cascaded in series. The circuit is easily implementable with 18 resistors, six capacitors, and six Op-Amps. The capacitors are standard available values and all the resistances can be obtained using trim pots. Apart from the rating of R–C values, another main component is Integrated Circuit (IC) TL-084 which is operational amplifier IC. It is quad single supply IC, i.e. a single IC has four Op-Amps. It requires a power supply of ±15 V. More details are available in Dhabale et al.²⁵ and Aware et al.²⁶

Table 1.

p–z pairs obtained using pole-zero approximation method.

	α = −0.2		α = −0.5		α = −0.8
i	z_i	p_i	z_i	p_i	z_i	p_i
1	−1.585	−1.02	−7.079	−2.613	−7.342	−1.267
2	−14.191	−9.133	−51.286	−18.928	−65.431	−11.288
3	−127.06	−81.773	−371.54	−137.12	−583.16	−100.61
4	−1137.6	−732.17	−2691.5	−993.34	−5197.4	−896.66
5	−10186	−6555	−19498	−7191.6	−46322	−7991.5
6	−91201	−58697	−141250	−52131	−412840	−71224

Table 2.

R–C values used for implementation of s^−0.5.

	α = −0.5
i,f	$R_{f}^{'} (k Ω)$	$R_{i} = R_{f} (k Ω)$	C_i (F)
1	223.9	382.7	1μ
2	30.90	52.83	1μ
3	9.08	15.52	0.47μ
4	8.66	14.80	0.068μ
5	8.13	13.89	10 n
6	5.1	8.71	2.2 n

The realized analog circuit for an integrator is shown in Figure 5. Experimental setup to test the fractional integrator circuits is shown in Figure 6. It consists of function generator, digital storage oscilloscope, and ±15 V power supply. The input signals are applied from the function generator to confirm the integrator behavior.

The circuit is tested for the square wave input. Figure 7 shows time response captured for fractional integrator circuits. The gains are set to get readable plots.

Learning: This experiment explains about the design of analog fractional integrator to the students. However, for analog implementation of each fractional integrator, different circuits are required. Component’s derating has occurred in the case of analog implementation which affects the results. Hence, digital implementation is suggested and practiced.

Lab 2. Design of digital fractional integrator

The discretization is a key concept in realization of a digital fractional integrator. For indirect discretization, two steps are needed, i.e. frequency-domain fitting in continuous time and then discretization of the fit continuous time transfer function.²⁸ The p–z pairs, obtained by proposed algorithm as shown in Table 1, are discretized using first-order hold, impulse invariant, zero-order hold, matched pole-zero pair, and “Tustin” approximation.³⁴ Bode’s plot for s^−0.5 digital fractional integrator is presented in Figure 8. It interprets that digital integrator with “Tustin” approximation matches with an integrator in continuous time and also it retains the stability.

The constant phase p–z interlacing algorithm for digital fractional integrator of α = −0.2, −0.5, −0.8 within the desired band of frequency ω_L = 100 rad/s and ω_H = 10000 rad/s gives discrete p–z pairs as in Table 3 with gain values of 0.11666, 0.0089841, and 0.00036712 respectively.

Table 3.

Discrete p–z pairs obtained using approximation.

	α = −0.2		α = −0.5		α = −0.8
I	z_i	p_i	z_i	p_i	z_i	p_i
1	−0.641	−0.492	−0.752	−0.446	−0.908	−0.562
2	0.892	0.506	0.763	0.471	−0.397	0.429
3	0.987	0.929	0.964	0.905	0.943	0.914
4	0.998	0.992	0.995	0.986	0.994	0.99
5	1	0.999	0.999	0.998	0.999	0.999
6	0.325	1	0.013	1	0.588	1

For the digital implementation of a fractional integrator, finite impulse response (FIR) filter structure is proposed. FIR filter gives good results while implementing on digital platform.³⁰ FIR approximations can be derived by choosing the order of filter “N.” The more terms an approximation uses, it will represent the original operator more accurately. Here, the order of filter “N” is chosen as 64, 128, and 1024.

Design example:

Consider the value of α; say −0.5.

Approximate it using the proposed method. The continuous time transfer function will come as

G (s) = \frac{(s + 141250) (s + 19498) (s + 2691.5) (s + 371.54) (s + 51.286) (s + 7.079)}{(s + 52131) (s + 719.6) (s + 993.34) (s + 137.12) (s + 18.92) (s + 2.612)}

(5)

Discretize equation (5) using “Tustin” approximation method and choosing sampling time T_s = 0.0001 s

G (z) = \frac{0.0089 (z + 0.752) (z - 0.763) (z - 0.964) (z - 0.995) (z - 0.999) (z - 0.013)}{(z + 0.446) (z - 0.471) (z - 0.905) (z - 0.986) (z - 0.998) (z - 1)}

(6)

Take the values of discrete p–z pairs and convert it into FIR filter form choosing order of filter N. By considering N = 64, the transfer function will come as shown in equation (7)

y [n] = b_{o} x [n] + b_{1} x [n - 1] + ⋯ + b_{n} x [n - N] = \sum_{i = 0}^{N} b_{i} x [n - i]

(7)

where x[n] is the the input signal, y[n] is the output signal, and b_i is the value of the impulse response at the ith instant for $0 \leq i \leq N$ .

The digital integrator is verified using FPGA-in-the-loop (FIL) wizard of MATLAB/Simulink. Experimental setup to test the digital circuits is shown in Figure 9. It consists of a DE2-115 FPGA development board and Intel Core i7 Processor. In Figure 10, the block diagram of FIL implementation is shown. Here, the digital integrator is realized using Altera’s DE2-115 FPGA development and education board. The digital integrator is successfully tested and the obtained results are presented. The digitally implemented fractional integrator with N = 64 gives the response as shown in Figure 11. N = 64 is chosen to reduce the computation burden, while the circuit is tested up to 1024. The similar response, as observed with analog circuit, is seen with a digital implementation which shows the potential of proposed algorithm and its implementation.

Learning: This experiment explains about the design of digital fractional integrator to the students. From the results obtained, it can be stated that the value of α indicates the strength of integration operation. For higher value of α, the output approaches to the output of integrator of order one, whereas, for small α, the output is nearer to the input signal.

Advantages of digital implementation of fractional integrator: An important advantage offered by digital realization is in the flexibility of its modifying controller characteristics. The ability to “redesign” the fractional operator/controller by changing software (rather than hardware) is an important feature of digital realization. Implementation of fractional operator for wide range of frequency is possible which was earlier constrained by the limitation of analog realization. However, the digital realization with digital processors, the range can be extended to the desired limit with virtually limitless computing power.

Limitations of digital implementation of fractional integrator: The main issues associated with the digital realization are related to the effects of sampling and quantization. The digital realization involves a cascade of analog-to-digital (A/D) conversion system followed by a digital processor which is, in turn, followed by digital-to-analog (D/A) conversion system. The A/D conversion process involves the sampling of analog signal at discrete instants of time separated by sampling time T_s. The D/A conversion process involves reconstructing continuous time signals from the samples given by the digital processor. The ill effects of sampling can be reduced, if not completely eliminated, by sampling at a very high rate.

With the availability of low-cost, high-performance digital processors and interfacing hardware, the implementation problems in digital realization do not pose a serious threat to its usefulness. The advantages of digital realization overweigh its implementation drawbacks for most of the applications.

Lab 3. Analog FO-PID controller for DC motor emulator

To verify the analog FO-PID controller, emulator of DC motor (Plant) is developed. More details are available in Aware et al.²⁶ Plant consists of DC motor and load with specification as speed = 2000 r/min, R_a = 2 W, L = 3 mH, J = 1.78e⁻⁴ kg m², K = 1.02, V = 24 V. The experimental setup is shown in Figure 12. The response of DC motor model with analog FO-PID controller is shown in Figure 13. The FO-PID performance indicates that the FO-PID with α = ±0.5 could make it possible to maintain the desired control on the output.

Learning: This experiment explains about the design of analog FO-PID controller to the students. In this experiment, DC motor emulator is used in place of actual DC motor to put more emphasis on controller implementation part. The results can be compared with integer-order PID controller also. The isodamping property⁵ of FO-PID controller can be observed by varying DC forward gain.

Lab 4. Digital FO-PID controller for hardware-in-the-loop (HIL) MagLev system

MagLev system is basically an electromagnetic system which levitates ferromagnetic objects in space by magnetic force induced due to the electric current flowing through coils around a solenoid. The continuous time approximation method is discretized and a novel digital FO-PID controller is developed. More details about the scheme are discussed in Chopade et al.⁷ This digital FO-PID controller is used to control highly nonlinear MagLev system in HIL mode as given in Figure 14. The controller is implemented in MATLAB/Simulink.

The performance analysis for digital PID and FO-PID controllers has been carried out. The desired and measured ball position control with PID controller is shown in Figure 15. The result in Figure 16 shows that the better control over position accuracy with lesser control efforts “u(t)” can be obtained with FO-PID controller.

Learning: This experiment explains about the design of digital FO-PID controller using MATLAB/Simulink. Control effort “u(t)” minimization is verified with this experiment. Control efforts are more in case of PID controller, hence, enveloped response is seen. The PID controller takes previous values in integration and works with instantaneous values at a point for differentiation. Whereas, the fractional-order integrations and differentiation take previous values into consideration with decreasing weights and therefore it has a memory effect in it. This memory effect gives ideal filtering action and thus, the smooth control signal is achieved using the FO-PID controller as it is filtered. Hence, FO-PID controller shows a clean signal. Fractional calculus-based system does the control action with a lesser effort than the conventional classical calculus-based controllers, therefore they are more efficient. Digital FO-PID controller is found to improve the position accuracy and control efforts of MagLev.

Lab 5. FIL digital FO-PID controller for BLDC motor

The speed control scheme for FO-PID controller-fed BLDC motor drive is shown in Figure 17.

A digital FO-PID controller-fed BLDC motor drive with four-switch inverter is modeled in this experiment. The FO-PID controller is used as a speed controller. As the speed reference is given, the FO-PID controller provides the control signal in accordance with the generated speed error. The generated reference current is given as input to the current controller. Further, the current controller provides switching pulses, which are obtained by comparing the reference input signal and the different modes provided by the motor module to operate the switches of an inverter. Here, the scheme is having FIL. The digital FO-PID controller is implemented on FPGA DE2-115 board. More details are available in Khubalkar et al.⁹ The FIL block is shown in Figure 18. The speed response of PID and FO-PID controlled scheme is displayed in Figure 19. The scheme with FO-PID controller is showing improved results than its integer counterpart.

Learning: This experiment explains about the design of digital FO-PID controller using FPGA to the students. In this experiment, conventional six-switch inverter topology can be used. As the design is digital, various forms of fractional-order controllers can also be verified.

Lab 6. Digital FO-PID controller for DC motor

Speed control scheme of buck converter-fed DC motor drive is shown in Figure 20. In Figure 21, experimental setup of digital FO-PID-fed DC motor is displayed.

Here, a reference speed of motor is selected as set point for the controller. The controller gives the control signal calculating the error generated in the control scheme. The PWM pulses are generated at particular duty cycle corresponding to the controller’s output. This signal operates the switch of DC–DC converter and controls the armature voltage of the DC motor. The controllers are implemented on TMS320f28377s DSP platform and used to control the speed of DC motor. More details about the scheme are available in Khubalkar et al.^8,35 Speed control of DC motor with reference speed of 1000 r/min is shown in Figure 22. The response improves considerably with FO-PID as shown in the results.

Learning: This experiment explains about the design of stand-alone digital FO-PID controller using DSP to the students. Fixed point and floating point DSPs can be used to implement the controller. By changing the coding of DSP, different forms of FO-PID controllers can be tested on the setup. The FO-PID controllers are robust against plant parameter variation. This property can be studied while performing this experiment on two different DC motors of same rating but having different plant parameters.³⁵

Utilization in research

All these experiments are effective in learning and research in the domain of fractional calculus. The various properties viz. iso-damping property, robustness against plant parameter variation, control effort minimization, etc. of fractional-order controllers are verified using the laboratory experiments. Undergraduates, postgraduates, and research scholars are the beneficiaries of this unique laboratory.

Conclusion

The research contribution of the laboratory is to provide efficient and practical way to implement fractional-order systems. This laboratory provides setup to overcome the barriers between simulations of fractional systems and real-time solutions. The pole-zero interlacing algorithm is realized and effectively used for developing the analog and digital fractional integrators. In the similar way, fractional differentiators are also developed and included in the laboratory. The analog circuit realization with commercial R–C components is achieved. FPGA and DSPs are very effective platforms for implementing fractional systems. The designed analog and digital FO-PID controllers are tested on various test benches. Analog controller is tested with DC motor emulator. Digital FO-PID is tested with MagLev as HIL. Then, the controller is tested with BLDC motor as FIL mode. Finally, stand-alone digital FO-PID is tested with 1.5 kW DC motor drive. All these experiments give a real-time exposure to fractional calculus and designed in the way that learner can understand the concepts effectively.

Footnotes

Declaration of Conflicting Interests

The author(s) declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

Funding

The author(s) disclosed receipt of the following financial support for the research, authorship, and/or publication of this article: This research was supported by Board of Research in Nuclear Sciences, project sanction no. 2012/36/69.

References

Elwakil

AS.

Fractional-order circuits and systems: an emerging interdisciplinary research area. IEEE Circuits Syst Mag 2010; 10: 40–50.

Alsaedi

Nieto

Venktesh

Fractional electrical circuits. Adv Mech Eng 2015; 7: 1–7.

Krishna

Studies on fractional order differentiators and integrators: a survey. Signal Process 2011; 91: 386–426.

Naumovic

MB.

A revisit to the fractional-order hold device. Electr Eng 2014; 96: 267–273.

Das

Functional fractional calculus. Berlin, Heidelberg: Springer, 2011.

Podlubny

Fractional-order systems and

P I^{λ} D^{μ}

controllers. IEEE Trans Automat Contr 1999; 44: 208–214.

Chopade

Khubalkar

Junghare

, et al. Design and implementation of digital fractional order PID controller using optimal pole-zero approximation method for magnetic levitation system. IEEE/CAA J Autom Sin 2018; 5 (5): 977–989.

Khubalkar

Chopade

Junghare

, et al. Design and realization of stand-alone digital fractional order PID controller for buck converter fed DC motor. Circuits Syst Signal Process 2016; 35: 2189–2211.

Khubalkar

Junghare

Aware

, et al. Modeling and control of permanent-magnet brushless DC motor drive using fractional order proportional-integral-derivative (FOPID) controller. Turk J Elec Eng Comp Sci 2017; 25: 4223–4241.

10.

Rezaei Estakhrouiyeh

Gharaveisi

Vali

Fractional order proportional-integral-derivative controller parameter selection based on iterative feedback tuning. case study: ball levitation system. Trans Inst Meas Control 2017; 40(6): 1776–1787.

11.

Swain

Sain

Mishra

, et al. Real time implementation of fractional order PID controllers for a magnetic levitation plant. AEU Int J Electron Commun 2017; 78: 141–156.

12.

Dwivedi

Pandey

Junghare

AS.

Stabilization of unstable equilibrium point of rotary inverted pendulum using fractional controller. J Frankl Inst 2017; 354: 7732–7766.

13.

Khubalkar

Chopade

Junghare

, et al. Design and tuning of fractional order PID controller for speed control of permanent magnet brushless DC motor. In: IEEE int conf on control, measurement and instrumentation, 8 January 2016, pp.320–326.

14.

Chopade

Khubalkar

Junghare

, et al. Fractional order speed controller for buck-converter fed DC motor. In: IEEE int conf on control, measurement and instrumentation, 8 January 2016; pp.331–335.

15.

Calderon

Vinagre

Feliu

Fractional order control strategies for power electronic buck converters. Signal Process 2006; 86: 2803–2819.

16.

Rapaic

Sekara

Novel direct optimal and indirect method for discretization of linear fractional systems. Electr Eng 2011; 93: 91–102.

17.

Biswas

Sen

Dutta

Realization of a constant phase element and its performance study in a differentiator circuit. IEEE Trans Circuits Syst II 2006; 53: 802–806.

18.

Verma

Pandey

Electronically tunable fractional order filter. Arab J Sci Eng 2017; 42(8): 3409–3422.

19.

Adhikary

Sen

Biswas

Practical realization of tunable fractional order parallel resonator and fractional order filters. IEEE Trans Circuits Syst I 2016; 63: 1142–1151.

20.

Chen

Zhang

, et al. A modeling and analysis method for fractional-order DCDC converters. IEEE Trans Power Electron 2017; 32: 7034–7044.

21.

Dimeas

Petras

Psychalinos

New analog implementation technique for fractional-order controller: a DC motor control. AEU Int J Electron Commun 2017; 78: 192–200.

22.

Debnath

Recent applications of fractional calculus to science and engineering. Int J Math Math Sci 2003; 54: 3413–3442.

23.

Freeborn

Maundy

Elwakil

AS.

Fractional-order models of supercapacitors, batteries and fuel cells: a survey. Mater Renew Sustain Energy 2015; 4: 9.

24.

Oustaloup

Levron

Mathiew

, et al. Frequency band complex noninteger differentiator: characterization and synthesis. IEEE Trans Circuits Syst I 2000; 47: 25–39.

25.

Dhabale

Dive

Aware

, et al. A new method for getting rational approximation for fractional order differintegrals. Asian J Control 2015; 17: 2143–2152.

26.

Aware

Junghare

Khubalkar

, et al. Design of new practical phase shaping circuit using optimal pole-zero interlacing algorithm for fractional order PID controller. Analog Integr Circ Sig Process 2017; 91: 131–145.

27.

Khanra

Pal

Biswas

Use of squared magnitude function in approximation and hardware implementation of SISO fractional order system. J Frankl Inst 2013; 350: 1753–1767.

28.

Machado

Discrete-time fractional-order controllers. Fract Calc Appl Anal 2001; 4: 47–66.

29.

Adhikary

Khanra

Pal

, et al. Realization of fractional order elements. INAE Lett 2017; 2: 41–47.

30.

Johansson

On FIR filter approximation of fractional-order differentiators and integrators. IEEE J Emerg Sel Topics Circuits Syst 2013; 3: 404–415.

31.

Anand

Farswan

Fernandes

Unique power electronics and drives experimental bench (PEDEB) to facilitate learning and research. IEEE Trans Educ 2012; 55: 573–579.

32.

Jiang

Carletta

Hartley

Implementation of fractional-order operators on field programmable gate arrays. In: J. Sabatier et al. (eds.), Advances in fractional calculus 2007; Dordrecht, Netherlands: Springer, 333–346.

33.

Muresan

Folea

Mois

, et al. Development and implementation of an FPGA based fractional order controller for a DC motor. Mechatronics 2013; 23: 798–804.

34.

Ogata

Discrete-time control systems. Englewood Cliffs, New Jersey: Prentice Hall, 1995.

35.

Khubalkar

Junghare

Aware

, et al. Demonstrative fractional order PID controller based DC motor drive on digital platform. ISA Trans 2017; (in press): 1–15. https://doi.org/10.1016/j.isatra.2017.08.019