Simulation analysis of a Multiple Bus Shared Memory Multiprocessor

Abstract

The past several years have brought the widespread acceptance of bus based shared memory parallel computer systems. There is a great deal of research which suggests that the limitations of single bus based interconnection networks prohibit effective use of more than perhaps 16 processors. Proposals have been made for several years [7] regarding the use of multiple buses to improve overall bandwidth.

In research conducted during the past two years we have studied the performance gains which could be made by providing additional buses to interconnect processors and memory. In this paper we will present the results of extensive trace driven simulation done using a sample workload. Because a detailed simulation model was created we are able to obtain fine grain detail regarding the operation of the system.

Keywords

multiprocessor architecture trace driven simulation performance analysis

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