The robustly resilient memory control problem is addressed for a class of switched systems with time delay under asynchronous switching. By resorting to the piecewise Lyapunov–Krasovskii functional, an asynchronous memory controller is designed to ensure the exponential stability of the closed-loop system. Here, the piecewise Lyapunov–Krasovskii functional means that for the activated subsystem, the associated Lyapunov–Krasovskii functional on the unmatched interval is different from that on the matched interval. Then an asynchronously resilient memory controller is derived to guarantee that the corresponding closed-loop system is robustly exponentially stable for all the admissible uncertainties. All the conditions are cast into the form of linear matrix inequalities. Finally, a numerical example is provided to illustrate the validity of the proposed results.
A switched system is a dynamical system that consists of a finite number of subsystems and a logical rule that orchestrates the switching between them. Due to its enormous theoretical and practical importance, increasing attention has recently been given to research on the stability analysis and controller synthesis of switched systems (Branicky, 1998; Hai and Antsaklis, 2009; Hespanha and Morse, 1999; Liberzon and Morse, 1999; Sun and Ge, 2005). However, time delays actually arise in a wide variety of applications modelled by switched systems, such as air traffic management, manufacturing systems, chemical processes, automotive engine control, and so on. We call this kind of system a switched system with time delay. It is important to study such systems due to the fact that time delay may deteriorate the performance of switched systems and even make them unstable. The past decades have seen considerable research activities into the modelling, analysis and synthesis of switched systems with time delay (Kim et al., 2006; Sun et al., 2006; Zong et al., 2008; Zong, 2013).
Controller design in most of the existing literature assumes that the switching between the controller and the system is synchronous. However, it takes time to identify which controller is activated in actual operation, which results in the asynchronous switching issue. Here, ‘asynchronous switching’ means that the switching of the controller lags behind or exceeds the switching of the system. Many related reports on this issue are available (see, for example, Wang et al., 2013, 2014; Zhai and Yang, 2013; Zhang and Gao, 2010). Zhang and Gao (2010) discuss asynchronously switched control for switched linear systems with an average dwell time in the continuous-time and discrete-time cases, respectively. However, for each activated subsystem, the same Lyapunov functions on the unmatched interval and matched interval are chosen. Zhai and Yang (2013) extend this result to switched time-delay systems, however, the Lyapunov functionals on the unmatched and matched intervals for each activated subsystem have the same form. Wang et al. (2013) further address dynamic output feedback control problems for switched delay systems under asynchronous switching, however, matrices in the Lyapunov functional on the unmatched interval are the same as those on the matched interval. This kind of candidate Lyapunov function or functional for each activated subsystem, to some extent, limits the application of these theorems, which leads to more conservativeness. This inspired the authors to adopt a piecewise Lyapunov functional for each activated subsystem, in order to relax the restriction on the Lyapunov functional. A piecewise Lyapunov functional means that for each activated system, the corresponding Lyapunov functional on the unmatched interval is different from that on the matched interval.
Typically, most of the results on the controller design can only deal with the situation in which the controller is precise, and exactly implemented, such as Sun and Ge (2005) and Zong et al. (2008). However, the controller should be able to tolerate some perturbations due to the finite word length in any digital system, A/D or D/A conversion, the imprecision inherent in analogue systems and other factors. Obviously, the relatively small perturbation of the controller gain might lead to performance degradation. This motivates us to design a controller that should be capable of tolerating some level of controller parameter perturbations. Such controllers are often termed ‘resilient’. Recently, some efforts have been developed to tackle the resilient controller design problem (Liu et al., 2014; Mahmoud, 2004; Park and Jung, 2004; Wang and Zhao, 2006). In particular, a resilient guaranteed cost controller is obtained for a class of uncertain dynamic systems with state delays in Park and Jung (2004). In addition, time delays frequently exist in state feedback. A controller is called a memory controller if it depends on the past state (Pan et al., 2008; Vu and Morgansen, 2010). To the best of the authors’ knowledge, no attention has been paid to designing an asynchronously resilient memory controller for a class of uncertain switched systems with time delay via the piecewise Lyapunov–Krasovskii functional technique.
In this paper, we address the robustly resilient memory control problem for a class of switched systems with time delay under asynchronous switching. There are two main contributions of this paper. On the one hand, considering that a resilient controller can tolerate some parameter perturbations and that an asynchronous memory controller has a broader range of applications, we design an asynchronously resilient memory controller to stabilize the given systems. This will increase the difficulty of the research but will have profound significance. On the other hand, the traditional piecewise Lyapunov–Krasovskii functional constructed in the existing literature often requires that the associated Lyapunov–Krasovskii functional for the activated subsystem on the unmatched interval has the same form as that on the matched interval. In contrast, piecewise Lyapunov–Krasovskii functionals constructed in this paper are different when the given switched systems are activated on the unmatched interval or the matched interval. Therefore, this implies that the main results in this paper have lower conservativeness compared with the existing results.
This paper is organized as follows. For the nominal form of an uncertain switched system with time delay, an asynchronous memory controller is initially established to make the given system exponentially stable by constructing a piecewise Lyapunov–Krasovskii functional. Then, based on the previous result, an asynchronously resilient memory controller is designed to guarantee the exponential stability of the closed-loop system for all the admissible uncertainties, which is able to tolerate some controller parameter perturbations. All the conditions are demonstrated in the form of linear matrix inequalities. Finally, a numerical example is given to illustrate the validity of the proposed results.
Notation. In this paper, notations are fairly standard. T stands for transposition of a matrix, denotes the n-dimensional Euclidean space, denotes the set of positive integers, ∥·∥ stands for the Euclidean vector norm, matrix means that P is positive definite (positive semi-definite), refers to , that is, is negative semi-definite matrix, I is identity matrix with an appropriate dimension, * denotes symmetric terms in symmetric matrices and means a block-diagonal matrix. denotes the minimum (maximum) eigenvalue of matrix P.
Problem formulation and preliminaries
Consider the following uncertain switched system with time delay
where is the state vector, is the control input, is the state delay, which is a time-varying continuous function, and is a continuously differential initial function of . The function , , specifying which subsystem will be activated, is a piecewise constant switching signal and continuous from everywhere. N denotes the number of subsystems. For , are known real constant matrices with appropriate dimensions. are uncertain real-valued matrices and satisfy
where are known real constant matrices. are unknown, real, and possibly time-varying matrices with Lebesgue-measurable elements and satisfy
Definition 1. A controller is memory if the controller depends on the past state.
Definition 2. If a controller is able to tolerate some level of controller parameter perturbations, then this controller is resilient.
Definition 3. For a switched system, controller is asynchronous if the switching instance of the controller lags behind or exceeds the switching instance of the system, that is, , where denotes the switching signal of the controller, and denotes the switching signal of the system.
Definition 4. For a switched system, a controller is called an asynchronously resilient memory controller if this controller is resilient, asynchronous memory.
Here, an asynchronously resilient memory controller is considered
where denotes the switching signal of the controller, is a controller gain to be designed, and is a controller gain variation which has two forms
additive controller gain variations
multiplicative controller gain variations
where are known real constant matrices. The time delay is assumed to satisfy the conditions
where h denotes the upper bound of time delay and stands for the upper bound of . They are two constant numbers.
Remark 1. Here, we assume that the switching instant of controller lags behind the switching instant of the system. Denote the switching instants of the system and the controller as, , and , respectively, where , stands for the time period in which the switching of the controller lags behind the switching of the system. is called a mismatched interval, and is called a matched interval.
Definition 5. (Sun et al., 2006) If the solution of the system satisfies for constants and , where , then the equilibrium of the system is said to be exponentially stable under the switching signal .
Definition 6. If the solution of the system satisfies for constants and , where , then the equilibrium of the system is said to be robustly exponentially stable for all admissible uncertainties under the switching signal .
Definition 7. (Hespanha and Morse, 1999) For a switching signal and any , , (), let denote the switching number of over the interval . If holds for , then is called ‘the average dwell-time’ and is ‘the chatter bound’.
Lemma 1. (Xie, 1996) Let , and F be real matrices of appropriate dimensions with . The following statements are equivalent:
;
there exists a scalar , satisfying .
Before ending this section, two important results of time-delay system are listed here.
Lemma 2. (Sun et al., 2006) Consider system with satisfying equation (6). For given constants , , and , if, there exist matrices , , , and such that the following inequalities hold
where , , , then there is a continuous functional
meeting with
Lemma 3. Consider system with delay satisfying equation (6). For given constants , , and , if, there exist matrices , , , , and such that the following inequalities hold
where , , , then there is a continuous functional
meeting with .
Proof. As with the proof of Lemma 2, it is omitted here.
The main task in this paper is to design an asynchronously resilient memory controller (3) for system such that the closed-loop system is robustly exponentially stable.
Design of an asynchronous memory controller
Consider the nominal form of system
where the definitions of vectors, matrices, parameters and functions are the same as those in . Here, an asynchronous memory controller is considered, which has the following form
In this section, the main task is to design the asynchronous memory controller (11) for to ensure that the resulting closed-loop systems is exponentially stable.
Remark 2. When or , the switching of the controller and the system is synchronous, that is . When , the switching of the controller fails to coincide with the switching of the system, that is, .
Theorem 1. Consider system with satisfying equation (6). For given constants , , , , if there exist constant , , a set of matrices , , , , , , , and such that for any , inequalities
where , , , , , hold, then under the asynchronous memory controller (11), system is exponentially stable with the following average dwell time scheme
where , denotes the total mismatched periods during and denotes the total matched periods during . Moreover, an estimate of the trajectory is given as follows
where
Proof. Substituting equation (11) into , the corresponding closed-loop systems gives
When , by Lemma 2 and from conditions (12) and (13), there exists in the form of equation (25) along the above closed-loop systems satisfying
where denotes the initial instant of the th controller which is activated in the interval . Similarly, by Lemma 3 and from equations (14) and (15), there exists in the form of equation (26) along system satisfying
where denotes the initial instant of the -th subsystem which is activated in the interval .
In the following, we shall pay more attention to the changes of at switching points. When the system switches at , from equations (16) and (17), we have
When the controller switches at , from equations (17) and (18), one gets
Subsequently, we shall discuss the upper and lower bound of in the mismatched period and the matched period , respectively.
From equations (32) and (33), it follows that where . By Definition 5, system is exponentially stable under asynchronous memory controller (11). The proof is completed.
Remark 3. The asynchronous stabilizing problem of switched systems has been much studied in the literature (Wang et al., 2013; Zhai and Yang, 2013; Zhang and Gao, 2010), but all the results in these papers have a common restriction, in that matrices in the Lyapunov functional on the unmatched interval are the same as those on the matched interval. This tight requirement limits their applications. In contrast, the piecewise Lyapunov–Krasovskii functional (24) constructed in the proof of Theorem 1 allows , , and , which means that Theorem 1 is less conservative.
Remark 4. Obviously, conditions in Theorem 1 are non-linear matrix inequalities, which are not easy to solve. The following theorem converts those non-linear matrix inequalities into linear matrix inequalities.
Theorem 2. Consider system with satisfying equation (6). For given constants , , , , if there exist constants , a set of matrices , , , , , , , , , , and such that for any , the following inequalities
where
hold, then under the asynchronous memory controller (11), system is exponentially stable with the average dwell time scheme (19). The controller gain is . Moreover, an estimate of the trajectory is given as equation (20).
Proof. Pre- and post-multiplying both sides of equation (34) by diag and denoting , , one easily derives equation (12). Similarly, one can see that equation (36) is equivalent to equation (14). By Theorem 1, the proof is completed.
Remark 5. It should be observed that the above matrix inequalities can be solved by resorting to the linear matrix inequalities toolbox. The steps are stated as follows.
Step 1: Choose constants , , .
Step 2: Inequality (34) is a linear matrix inequality. We can solve , , , , , , , and then verify . From equations (41) to (44) and , values of , , , , , , , , can be solved, which are used to verify equation (35)
Step 3: Choosing a positive constant and substituting the value of calculated in step 2 into equation (36), inequality (36) becomes a linear matrix inequality, which can be used to solve , , , , , , , and then verify . From equations (45) to (48), it is easy to derive the values of , , , , , , , , which can be utilized to verify equation (37).
Step 4: Substituting the values of calculated in step 2 and , , calculated in step 3 into equations (38) to (40), we can compute values of and and verify .
Step 5: Choosing a scalar (), a value of and an estimate of the trajectory can be easily obtained.
In the previous section, an asynchronous memory controller was obtained. In this section, we will design an asynchronously resilient memory controller for system based on Theorem 1.
Theorem 3. Consider system with satisfying equation (6). For given constants , , , , if there exist constants , , a set of matrices , , , , , , , and such that for any , the following inequalities
where
hold, then, under an asynchronously resilient memory controller (3), system is robustly exponentially stable with the average dwell time scheme (19). Moreover, an estimate of the trajectory is given as equation (20).
Proof. Based on Theorem 1, it is easy to obtain Theorem 3 by replacing with , respectively.
Remark 6.Zhai and Yang (2013) designed an asynchronously resilient memory controller for switched linear systems, with a tight restriction in the conditions of the main results. Here, we not only relax this condition but also design an asynchronously resilient memory controller such that the closed-loop system is robustly exponentially stable for all admissible uncertainties.
In Theorem 3, there exist uncertain terms , , which make it hard to solve the problem. Therefore, the main task in the following is to remove , , from the conditions, which will be presented in Theorem 4 with additive controller gain variations (4) and in Theorem 5 with multiplicative controller gain variations (5).
Theorem 4. Consider system with satisfying equation (6). For given constants , , , , if there exist constants , positive constants , a set of matrices , , , , , , , , and such that for any , the following inequalities
where
hold, then under asynchronously resilient memory controller (3) with additive controller gain variations (4), system is robustly exponentially stable with the average dwell time scheme (19). The controller gain is . Moreover, an estimate of the trajectory is given as equation (20).
Proof. Pre- and post-multiplying both sides of equation (51) by diag and denoting , , one derives
Similarly, one can see that equation (53) is equivalent to equation (50). By Theorem 3, the proof is completed.
Theorem 5. Consider system with satisfying equation (6). For given constants , , , , if there exist constants , , positive constants , , a set of matrices , , , , , , , , and such that for any , the following inequalities
where
hold, then under the asynchronously resilient memory controller (3) with multiplicative controller gain variations (5), system is robustly exponentially stable with the average dwell time scheme (19). The controller gain is . Moreover, an estimate of the trajectory is given as equation (20).
Proof. Similar to the proof of Theorem 4, this proof can be obtained by replacing , , of the proof of Theorem 4 with , , , respectively.
A numerical example
Example. Consider the time-delay switched system with parameters given below.
and equation (54) is true. Substituting equations (68) and (70) into equations (55) to (57), it is easy to calculate and satisfying . Choose satisfying . From equation (19), we derive , and . The state trajectory of the closed-loop system, the switching signals of the system and the controller and the output of the controller are depicted in Figure 1. From Figure 1(a), the state trajectory of the system tends to the origin under the designed asynchronously resilient memory controller, which shows the correctness of Theorem 4. From Figure 1(c), it is obvious that the length of the matched interval is larger than the length of the mismatched interval to guarantee the exponential stability of the closed-loop system, which coincides with the fact that . From Figure 1(b), it can be observed that there is no fluctuation in the output of the controller, thus the designed controller can be operated well for the example.
Curves of the closed-loop system state trajectories, the output of the controller, and the switching signals of the system and the controller.
Conclusions
In this paper, we have investigated the robustly resilient memory control problem for uncertain switched systems with time-delay under asynchronous switching. We have designed an asynchronously resilient memory controller to ensure that for all the admissible uncertainties the closed-loop system is robustly exponentially stable under the designed switching laws. Here, the piecewise Lyapunov–Krasovskii functional method and the average dwell time method have been utilized. Moreover, an estimate of the trajectory is presented. Finally, a numerical example has been given to illustrate the effectiveness of the proposed approach.
In this manuscript, the robustly resilient memory control problem is only considered for continuous-time switched delay systems under an asynchronous switching scheme. In the future, we shall concentrate on the robustly resilient memory control problem for discrete-time switched systems under the asynchronous switching case.
Footnotes
Declaration of conflicting interest
The authors declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.
Funding
The authors disclosed receipt of the following financial support for the research, authorship, and/or publication of this article: This work was supported in part by the National Natural Science Foundation of China (grant numbers 61273123, 61304059 and 61573041), in part by the Program for New Century Excellent Talents in University (grant number NCET-13-0878) and in part by the Program for Scientific Research Innovation Team in Colleges and Universities of Shandong Province.
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