A switch-source cell-based cascaded multilevel inverter topology with minimum number of power electronics components

Abstract

Multilevel inverters are a new generation of DC–AC converters at medium and high voltage and power levels. In this paper, a new single-phase cascaded multilevel inverter is presented. For this purpose, a new basic cell is presented at first. Then, the new multilevel inverter structure is yielded by series connection of these cells. The proposed new cell is only capable of generating positive voltage levels, and therefore, to produce zero and negative voltage levels, the proposed structure is constructed based on H-bridge module. In order to reduce the maximum blocking voltage especially on H-bridge switches, the cascaded connection of the proposed converter is investigated. A comprehensive comparison is carried out between the proposed multilevel inverter with the classical and recently introduced structures in terms of the number of switching devices, the number of drivers, the total blocking voltage of the switches as well as the loss and efficiency. The accuracy of the proposed inverter’s performance is simulated in MATLAB/Simulink in symmetric and asymmetric topologies for a 17-level and 23-level output voltage respectively, and then evaluated by the laboratory prototype.

Keywords

Multilevel inverter switch count gate driver count power loss

Introduction

The advent of gate-controlled power electronic instruments and the ever-expanding technology has caused a widespread use of power electronics and power converters in a variety of cases including industry, commerce, communications, aerospace, renewable energy systems and power grids (Mohan et al., 2003). Converters that transform direct current (DC) into alternating current with the desired amplitude and frequency are called inverters. Various applications of inverters can be mentioned in industrial applications connected to the grid, especially to distribution networks such as reactive power compensators, DVRs, active filters, photovoltaic and wind renewable energy systems, uninterruptible power supplies, variable-speed asynchronous motor drivers, FACT devices, electric vehicles, etc. (Babaei et al., 2016). A multilevel converter is a power electronic system that combines and produces a desired multilevel output voltage from multiple DC voltages as input (Majareh et al., 2019). Two-level inverters have disadvantages such as low-quality output voltage and current, high output power ripple, low amplitude of the fundamental component, low efficiency, high switching loss, higher dv/dt, high stress on power switches and high electromagnetic interference (Hosseinpour et al., 2020). Multilevel inverters have removed the mentioned disadvantages. In addition, the voltage and power range of the multilevel inverters are higher than the two-level inverters (Kangarlu et al., 2012; Seifi et al., 2020).

The classical multilevel inverters are divided into three main categories: (a) neutral point clamped (NPC), (b) fly capacitor (FC) and (c) cascade H-bridge (CHB). The first and second category, along with the advantages mentioned above, have challenges and disadvantages such as the large number of flying capacitors and the complexity of balancing their voltage, the high use of sensors and their sophisticated control, the complexity of balancing the DC link capacitors, and so on. The third class is the classical CHB inverter which is widely used in industry. The benefits of CHB inverters include modularity, easy control and low voltage stress of the switches. The main disadvantage of this structure is the large number of semiconductor power switches and driver circuits especially at higher levels that directly increase cost and volume. These disadvantages result in increased loss, volume and cost, and lead to lower efficiency. Because of these disadvantages, scholars have turned to new multilevel inverter structures.

The output voltage waveform quality of multilevel converters increases with increasing number of levels. Also, the output filter can be removed by this increscent. In classic inverters, by increasing the number of output levels, the number of switching devices rises dramatically. This problem escalates the complexity and cost of the system, which can reduce the reliability and performance and decrease efficiency considerably. Therefore, in order to produce a waveform with better quality, it is attempted to minimize the number of switches and gate driver circuits that include the most cost (Behara et al., 2018; Hsieh et al., 2016; Sandeep and Yaragatti, 2018). Reducing the number of switches can lead to increased system efficiency, which is an important parameter in the selection of converter for industrial applications.

Design approaches for new structures can be divided into three categories: topological changes (Ebrahimi et al., 2012; Hosseinpour et al., 2020), using asymmetric resources (Najafi and Yatim, 2012; Pereda and Dixon, 2011), and combination of topological changes and asymmetric adjustment of input sources (Gupta and Jain, 2012; Ounejjar et al., 2012). The second and third batches produce a higher number of output voltage levels than the first one, but they result in greater voltage stress and disparate power loss as well as power distribution on switches.

Distributed energy resource integration into low/mid voltage grids can be considered as an application of the proposed multilevel inverter. High-quality output voltage of the inverter causes to reduce massive filters utilizing. Size, cost, and weight of the filters are reduced by applying the inverter. Thereby, the proposed structure may be a good choice in connecting of the PV sources, where several DC sources are available. Also, the proposed structure in three-phase mode can be utilized for electric motor drive applications. In addition to produce high/mid power, producing voltage with low dv/dt, which leads to high performance of the motors, is a significant advantage of the multilevel inverters. It is important to mention that in switch count and driver aspects, the proposed structure has better condition than other advanced structures. The most important advantage of the proposed structure is lower cost, size, and weight in comparison with similar novel structures.

For medium voltage drives, high quality of voltage and current waveforms both at the input and output terminals is important. The waveforms are affected by the following factors: (a) the topology used; (b) the application; (c) the control algorithm; (d) the size of the filter; and (e) the choice of switching frequency (Abu-Rub et al., 2010). It should be noted that reducing of switching losses of semiconductor devices allows the maximum output power to be increased. On the other hand, a reduction in switching frequency increases the harmonic distortion of the line and motor side waveforms. The multilevel inverters have the ability to deliver waveforms with a better harmonic spectrum and limit the motor-winding insulation stress. However, the increasing number of switching devices tends to reduce the overall reliability and efficiency of the power converter. On the other hand, an inverter with a low number of output levels would need a large and expensive LC output filter to reduce the motor-winding insulation stress (Krug et al., 2007). Thus, the challenge is to reduce waveform distortions when a low switching frequency is used, to ensure high power quality, and to allow fast dynamic responses at very low switching frequencies. Such goals may be achieved by constructing the multilevel structure.

In low voltage networks, the main purpose of the multilevel inverter applications is quality improvement of the injected voltage and current. For instance, a multilevel inverter structure has been proposed which is able to integrate renewable energy resources into low voltage grids (Agrawal and Jain, 2017). By applying the multilevel inverter, the conversion system can ignore the connecting transformer. Also, heavy and bulky filters are not required due to the high quality of the produced voltage (Agrawal and Jain, 2017). Desirable voltage production with low switching frequency is another advantage of the multilevel inverters. Although there are no limitations for switching frequency in low voltage and power, utilization of the low switching frequency multilevel inverter causes total efficiency of the converter to increase (Villanueva et al., 2009). An inverter with 27-level output voltage as static var compensator (SVC) and active power filter has been used at low voltage grid (Flores et al., 2008). This multilevel inverter can process PV power and integrate it into low voltage network. Another 7-level structure has been used for injecting PV power into low voltage grid with high voltage quality and low THD (Vahedi et al., 2018).

This paper presents an improved structure of H-bridge-based voltage source multilevel inverters with the aim of reducing power electronic devices, which has fewer power switches than classic structures and recent researches. This switch number difference is observed more clearly at higher levels and makes the proposed structure more tangible. This structure uses an improved basic cell that is capable of producing two voltage levels with one switch less than the existing basic cell. This approach reveals a significant decrease in the required number of power switches compared to classic topologies and similar researches. In order to reduce the maximum blocking voltage of H-bridge switches, the cascaded connection of proposed inverter is introduced. The proposed structure for symmetric topology has two similarities to the symmetric CHB structure: (a) it requires separate DC input voltage; and (b) output levels of the voltage are constructed by combining DC input sources. The proposed structure is a suitable and good choice for mid voltage application. Simultaneously, it can be applied at low voltage for improving quality of the voltage.

The structure of this paper is as follows. The second section presents the general structure of the proposed topology. Computation of casualties and comparison of proposed structure loss with some similar researches is then presented. The following section compares the proposed structure with similar researches in terms of the number of switching devices, the number of drivers and the total blocking voltage of the switches. The results of simulations and laboratory implementations are presented in the penultimate section. Finally, the conclusion of the paper is summarized.

Topology of the proposed multilevel inverter

In this section, the existent and the proposed basic cells are introduced and the principles of performance of the proposed generalized structure for both symmetric and asymmetric topologies along with mathematical equations are explained.

Basic cell

In this paper, the proposed multilevel converter uses the extension of an improved basic cell. Figure 1(a) displays the basic cell presented in Babaei et al. (2015). It consists of three DC voltage sources and five power switches that can produce two positive voltage levels, +2V_DC and +3V_DC. In Figure 1, all voltage sources are considered to be equal. All of them produce V_DC (i.e. V₁ = V₂ = V₃ = V_DC). Power electronic switches can be implemented using a transistor (such as MOSFET or IGBT) with an anti-parallel diode. Figure 1(b) demonstrates the proposed basic cell, which is capable of producing the same voltage levels compared to the basic cell presented in Babaei et al. (2015) by reducing a switch, that is, the S₃ switch. In other words, as shown in Figure 1, switch S₃ has been eliminated in the proposed cell, which exists in cell of Babaei et al. (2015). Therefore, the proposed basic cell produces the same voltage level by one switch less than the structure of Babaei et al. (2015). It causes to reduce a switch and a driver in the proposed cell in comparing with cell of Babaei et al. (2015). Reducing the switch and driver count results in lower cost for the proposed structure. Also, this switch count reduction leads to switching and conducting loss reduction and efficiency improvement.

Figure 1.

Basic cells: (a) presented in Babaei et al. (2015), (b) proposed.

Table 1 illustrates the output voltage of the proposed basic cell in possible states. The important point about this cell is that it only produces positive voltage levels, +2V_DC and +3V_DC.

Table 1.

Different states of the proposed basic cell.

Mode	S₁	S₂	S₃	S₄	v _o
1	0	0	0	1	0
5	1	0	1	0	2V_DC
6	1	1	0	0	3V_DC

Generalized structure

The generalized structure of the proposed multilevel inverter is demonstrated in Figure 2. Since the produced voltages of the proposed cells consist of positive values, the proposed structure is based on the H-bridge module whose task is to change the polarity of the output voltage as well as producing the zero-voltage level. The structure includes one/several proposed cell/cells, which are connected together in cascaded manner. In addition to the proposed cell, another cell, which includes voltage source V₄, S₅ and ${\bar{S}}_{5}$ switches, is considered. Since the proposed cell can produce 2V_DC and 3V_DC, then for producing 1V_DC voltage level as well as more voltage levels, voltage source V₄ and V₅ are considered in the structure. Note that all voltage sources are equal (V_DC) in the symmetric topology. This structure has fewer switches on equal levels of the output voltage compared to the reference structure and the most recent ones.

Figure 2.

Proposed generalized structure.

According to Figure 2, the voltage across the H-bridge module, which is represented by v_o,dc, is obtained from the sum of the voltage of the basic cells (v_o,n), $v'_{o}$ and V₅ according to (1).

v_{o, dc} = v_{o, 1} + v_{o, 2} + . . . + v_{o, n} + v'_{o} + V_{5}, n \geq 1

(1)

In the above equation n represents the number of basic cells used in the proposed multilevel inverter structure. v_o,dc denotes a positive DC value that this voltage or its inverse can be applied to the load by the H-bridge module. It is worth noting that the zero voltage level can also be generated by H-bridge switches.

Symmetric topology

For the symmetric topology, the DC sources can be considered as $V_{1, n} = V_{2, n} = V_{3, n} = V_{4} = V_{5} = V_{DC}, n \geq 1$ . In this case, the peak output voltage is expressed by (2) and the number of levels synthesized by the proposed structure with the equal voltage sources can be expressed by (3) in which n represents the number of proposed basic cells.

V_{o, max}^{sym} = (3 n + 2) . V_{DC}

(2)

N_{level}^{sym} = 6 n + 5

(3)

The number of required switches (N_Switch), the number of drivers (N_Driver) and the total blocking voltage (TBV) for the proposed structure in symmetric topology can be expressed by (4), (5) and (6).

N_{switch}^{sym} = 4 n + 6

(4)

N_{driver}^{sym} = 4 n + 6

(5)

{TBV}^{sym} = (19 n + 10) . V_{DC}

(6)

The cost of a converter can be determined by the three parameters that are mentioned above. The lower amount of these parameters will result the lower amount of overall cost of the converter. In the meantime, the blocked voltage by the current passing through the switch and its switching frequency are the key parameters in selecting the switches. Therefore, in order to calculate the switching block voltage index, the value of the blocking voltage by each of the switches or maximum blocking voltage (MBV) should be considered. As shown in Figure 2, the blocked voltage values by each of the switches are as follows:

V_{S_{5}} = V_{{\bar{S}}_{5}} = V_{4}

(7)

V_{S_{1, n}} = V_{1, n} + V_{3, n}, n \geq 1

(8)

V_{S_{2, n}} = V_{S_{3, n}} = V_{2, n}, n \geq 1

(9)

V_{S_{4, n}} = V_{1, n} + V_{2, n} + V_{3, n}, n \geq 1

(10)

V_{S_{6}} = V_{{\bar{S}}_{6}} = V_{S_{7}} = V_{{\bar{S}}_{7}} = \sum_{i = 1}^{n} v_{o, i} + v'_{o} + V_{5}, n \geq 1

(11)

Where $V_{S_{i}}$ and $V_{{\bar{S}}_{i}}$ are the maximum blocking voltage by switches $S_{i}$ and ${\bar{S}}_{i}$ . Also, $V_{S_{k, n}}$ is the maximum blocking voltage by switch $S_{k, n}$ .

Asymmetric topology

Various strategies can be defined for asymmetric DC source topology. In this paper, the binary method is applied to determine the DC sources values of various cells for the proposed multilevel inverter. In this method, the DC sources of the first cell are equal to V_DC, the second ones are equal to 2V_DC and the DC sources of the third cell are selected equal to 4V_DC. The DC sources values in this method can be represented by (12). The peak of output voltage can be expressed by (13) and the number of levels that can be synthesized for the proposed structure by (14).

V_{Cell}^{asy} = 2^{n - 1} . V_{DC}, n \geq 1

(12)

V_{o, max}^{asy} = 2 (3 (2^{n + 1} - 1) + 4) + 1, n \geq 1

(13)

N_{level}^{asym} = 3 (2^{n + 1} - 1) + 4, n \geq 1

(14)

In the above equations, n represents the number of basic cells. The number of required switches (N_Switch), number of drivers (N_Driver) for the proposed structure in asymmetric voltage source topology can be expressed in terms of (15) and (16):

N_{switch}^{asym} = 4 n + 6

(15)

N_{driver}^{asym} = 4 n + 6

(16)

In the above equations, n represents the number of basic cells. Although, in asymmetric topology higher voltage levels are produced than symmetric topology, they are much more susceptible to higher voltage stress and switch loss. In addition, producing DC voltages with different values are more complex.

Cascaded topology

High rated voltage values of H-bridge switches in topologies based on H-bridge limits the applications of such structures. These switches should withstand the sum of input voltages. In other words, their blocking voltage is equal to the sum of input voltages. The cascaded configuration can be used to deal with this problem. In this configuration, the output voltage is equal to the sum of the generated voltages of cascaded cells. Therefore, the voltage acroos the H-bridge switches will be divided among these cells. This prevents the increase of switch ratings. The cascaded configuration of the proposed topology is shown in Figure 3.

Figure 3.

Cascaded configuration of the proposed inverter.

In this configuration the output voltage (V_o), switches count (N_Switch) and diodes count (N_Driver) to generate N levels of output voltage can be expressed by (17), (18) and (19).

V_{o}^{cas} = v_{o, 1} + v_{o, 2} + . . . + v_{o, Z}

(17)

N_{switch}^{cas} = 10 Z

(18)

N_{driver}^{cas} = 10 Z

(19)

where Z is the number of cascaded cells. By using this configuration, unequal DC sources can be employed for different cells. As a result, the asymmetric implementation of the topology becomes possible. However, although in asymmetric implementation higher number of output voltage can be generated but the voltage stress and power losses of switches are more and the modularity of the converter decreases. Moreover, generating DC voltages with different values and also controlling the converter becomes more complicated.

Loss calculations

Power loss is a major parameter in the design of multilevel converters due to the high use of switches. This loss is divided into two main parts: conductive loss (P_Con) and switching loss (P_Sw). Conductive loss occurs over a basic period that drives the switch and diode. P_Con is the sum of conductivity loss for IGBT (P_C,IGBT) and diode (P_C,D) according to (20) and (21) (Ali et al., 2018).

P_{C, IGBT} = \frac{N_{IGBT} (t)}{2 π} \int_{0}^{2 π} V_{on, IGBT} . I + R_{on, IGBT} . I^{β + 1} d (ω t)

(20)

P_{C, D} = \frac{N_{D} (t)}{2 π} \int_{0}^{2 π} V_{on, D} . I + R_{on, D} . I^{2} d (ω t)

(21)

which V_on,IGBT and R_on,IGBT are IGBT voltage drop in ON mode and IGBT resistance, respectively. Also, V_on,D and R_on,D are diode voltage drop in ON mode and diode resistance, respectively. In addition, N_IGBT(t) and N_D(t) are the number of IGBTs in ON mode and reverse parallel diodes in conduction mode. The β coefficient depends on the IGBT specifications. The transient current passing through semiconductor device is assumed to be a sine wave ( $I = I_{m} \sin (ω t)$ ) which I_m is the maximum current passing through the device. The other part of the power loss is the switch loss that occurs when switches are turned ON and OFF, as follows (Ali et al., 2018):

P_{Sw, ON} = \frac{N_{ON}}{2 π} \int_{0}^{t_{ON}} V (t) . I (t) dt = \frac{V_{Sw} . I . T_{ON} . N_{ON}}{6 T}

(22)

P_{Sw, OFF} = \frac{N_{OFF}}{2 π} \int_{0}^{t_{OFF}} V (t) . I (t) dt = \frac{V_{Sw} . I . T_{OFF} . N_{OFF}}{6 T}

(23)

where N_ON and N_OFF are the number of on and off mode of a switch during a fundamental cycle. Also, T_ON and T_OFF turn switches ON and OFF and V_Sw is the maximum voltage on the switches. Total power loss P_Loss by summing (20)–(23) can be obtained as follows:

P_{Loss} = P_{C, IGBT} + P_{C, D} + P_{Sw, ON} + P_{Sw, OFF}

(24)

Then the efficiency of the multilevel converter is calculated as follows:

η = \frac{P_{Out}}{P_{In}} = \frac{P_{Out}}{P_{Out} + P_{C, IGBT} + P_{C, D} + P_{Sw, ON} + P_{Sw, OFF}}

(25)

The connection temperature (T_j) of each switch is determined using the method described above. Obviously, T_j is proportional to power loss, which means that the loss is higher due to high temperatures. The junction temperature of IGBT (T_IGBT,jun) and diode (T_Diode,jun) are calculated using (26) and (27) (Ali et al., 2018) and the ambient temperature $T_{a} = 25^{°} C$ .

T_{IGBT, jun} = P_{Loss, IGBT} . (\frac{R_{Th, JC, IGBT}}{k} + \frac{R_{Th, JH, IGBT}}{k}) + T_{a}

(26)

T_{Diode, jun} = P_{Loss, Diode} . (\frac{R_{Th, JC, Diode}}{k} + \frac{R_{Th, JH, Diode}}{k}) + T_{a}

(27)

where k is the coefficient of current that depend on the number of parallel IGBTs, which in this case k is equal to 1. P_Loss,IGBT and P_Loss,Diode are the total power loss of the IGBT and diode, respectively. The values of the junction temperature to the case (R_Th,JC) and the junction temperature to the heatsink (R_Th,JH) are extracted from the IGBT datasheet.

Loss simulation and efficiency calculation of proposed converter as well as its devices temperature evaluation is carried out based on the manufacturer’s data in Matlab/Simulink environment using Equations (20)–(27). The IGBT switch IKFW60N60DH3E (600v 50A) is used to model the switch. The flowing current of switches and the blocking voltage of each switch are considered in the loss simulation. The simulation is carried out for an 11-level proposed topology using phase-shifted PWM (PS-PWM) and output voltage peak of 250V. The power losses and efficiency as well as switches temperature are calculated for different output powers and PFs. The switch temperature depends on the flowing current of switch as well as its switching loss. The results of these calculations are shown in Figure 4(a)–(d). The load power factor is increased from case (a) to case (d) in Figure 4. The summarized results of power loss and converter efficiency for assumed cases (a)–(d) are illustrated at Figure 5. According to this figure, increasing the power factor will result in higher efficiency.

Figure 4.

Simulation results of power loss for various output power: (a) 3748W, (b) 2098W, (c) 514W, (d) 139.1W.

Figure 5.

Summarized results for power loss and efficiency of proposed converter for assumed cases (a)–(d).

The losses simulation of the proposed structure as well as other comparable structures is provided for an 11-level inverter. This inverter containing a basic proposed cell with symmetric DC sources is controlled using SPWM phase shift modulation technique with 350Hz switching frequency at 80% of the switch’s nominal values (i.e. at 480V and 40A) at 8617W input power for resistive load. The results of the power loss of each switch are presented individually in Figure 6. In addition, Figure 6 demonstrates the efficiency values of the proposed structure and compared structures under the same conditions. As can be seen in Figure 6, the proposed structure yields a higher value of efficiency than the recently proposed structures.

Figure 6.

Simulation results of power loss and efficiency of the proposed structure and comparison with recent structures.

Comparison with other structures

In this section, the proposed structure is compared with similar recent researches on symmetric voltage sources for generating identical voltage levels. Since there are several strategies for asymmetric topologies, comparisons have been made for one asymmetric strategy. The most important comparative parameters discussed in multilevel inverters are the number of switches, the number of drivers and the total blocking voltage (TBV). Equation (28) describes calculation of the total blocking voltage in terms of the maximum blocking voltage (MBV) of each switch.

TBV = \sum_{Switch = 1}^{M} MB V_{Switch}

(28)

The cost of multilevel inverters is directly related to the mentioned comparative parameters. In other words, the higher the number of switches, drivers and TBVs, the higher the cost of the inverter. Researchers have always sought to provide a structure that is less costly to implement in the industry. The volume of the inverter is also related to the number of devices: the smaller the number of devices, the lower the inverter’s volume to increase its performance.

The proposed structure has a lower number of switches for identical output voltage levels than the recent developed one. A comparison of the number of switches between proposed structure and other symmetric multilevel converters for different voltage levels is presented in Figure 7. The lower the slope of the curve in Figure 7, the lower the switch and the smaller the volume required for the structure by increasing the number of output voltage levels. The CHB structure is a set of several H-bridge units, each consisting of a DC source and four switches. In the CHB structure, four switches are added to the structure for increasing one H-bridge module (increasing two levels to output levels). Indeed, the slope of the switch diagram relative to the output voltage level in the symmetric CHB structure is 2. In almost all presented structures, the slope of this graph is equal to 1. In other words, two switches are added to the structure for increasing two voltage levels. The slope of this diagram for the proposed structure is equal to 0.75. In other words, in order to increase six levels to the output voltage levels, you only need to add four switches to the proposed structure. It is clear that the proposed structure reveals a significant improvement in reducing the number of switches, especially at high output voltage levels. Obviously, the number of gate drivers and other supplementary components such as heatsinks and snubbers are approximately proportional to the number of switches, and therefore they will be reduced in the proposed structure.

Figure 7.

Comparison of switch count in different multilevel inverter structures.

Figure 8 displays the comparison of the number of required drivers in the proposed structure and the most recently presented structures. As can be seen, the structures presented in Alishah et al. (2016), Ebrahimi et al. (2012), Jayabalan et al. (2017), Kangarlu et al. (2012) and Samsami et al. (2017) are a little superior to the proposed structure in term of the number of drivers due to using bidirectional switches which results lower number of gate drivers. However, the proposed structure is significantly superior to the mentioned structures in terms of the number of switches and the total blocking voltage (TBV) at equal output voltage levels. The TBV values of the proposed structure and the comparable structures are visible under the same conditions for the 17-level output voltage in Table 2.

Figure 8.

Comparison of gate driver count in different multilevel inverter structures.

Table 2.

Comparative parameters of multilevel inverters in symmetric 17-level topology.

	N_Driver	TBV(*V_DC)	N_source	N_Diode	N_Switch	N_level
Symmetric CHB	17	32	0	8	32	32
(Babaei et al., 2015)	17	18	0	8	52	18
(Alishah et al., 2016)	17	20	0	8	58	14
(Jayabalan et al., 2017)	17	22	8	0	14	60
(Dhanamjayulu and Meikandasivam, 2018)	17	20	8	16	18	52
(Oskuee et al., 2015)	17	18	8	0	18	50
(Banaei et al., 2014)	17	18	8	0	18	44
(Samsami et al., 2017)	17	18	0	8	88	12
(Ali et al., 2019)	17	18	0	8	34	18
(Saeedian et al., 2017)	17	20	16	8	52	20
(Kangarlu et al., 2012)	17	18	0	8	64	14
(Ebrahimi et al., 2011)	17	20	0	8	48	20
(Ebrahimi et al., 2012)	17	20	0	8	48	13
(Siddique et al., 2019)	17	18	0	8	74	12
Proposed	17	14	0	8	48	14

Table 2 presents a more detailed examination of the proposed structure and similar structures for the symmetric 17-level output voltage. Table 2 indicates that the number of proposed structure parameters for 17-level output is smaller than compared structures. Also, the TBV value for the proposed structure is slightly more than only three compared structures including symmetric CHB as well as structures presented in Ali et al. (2019) and Banaei et al. (2014). It should be noted that the mentioned structures contain more power switches and drivers.

Simulation and implementation results

In this section, the simulation and implementation results of the proposed multilevel inverter are presented. There are several methods for switching multilevel inverters that fall into two general categories of low frequency switching and high frequency switching methods. High frequency modulation methods include sinusoidal PWM and space vector modulation (SVM) techniques. On the other hand, low frequency switching methods include staircase switching, fundamental frequency switching, active harmonic elimination, nearest level modulation (NLM) and selective harmonic elimination (SHE) methods. The proposed topology can be well adapted to either of these methods. To evaluate the performance of the proposed structure, two basic cells are considered according to Figure 9. The proposed structure for the 17-level symmetric and 23-level asymmetric topologies is simulated by the MATLAB/Simulink based on NLM method.

Figure 9.

17-level symmetric and 23-level asymmetric topology for simulation and experimental setup.

In order to validate the simulation results, a laboratory prototype of the proposed 17-level symmetric and 23-level asymmetric topologies are implemented by the nearest level modulation (NLM) method. Table 3 demonstrates the simulated system as well as the laboratory implementation information for the proposed structure. Figure 10 displays the circuit of the laboratory prototype.

Table 3.

Specifications of simulated system and laboratory prototype.

Parameters	Specification
DC sources	6-12V
Output voltage (peak)	64-66V
Output current (peak)	3A
R_Load	$15 Ω$
L_Load	48mH
MOSFETs	IRFP 450
GATE driver	TLP 250
Diodes	1N5408
Controller	Arduino Mega 2560

Figure 10.

Schematic of the proposed structure’s practical circuit.

Separating DC voltage sources as input sources are utilized during implementation of the proposed structure. In practice, these DC voltage sources may be yielded from AC energy resources. If an AC source is available, required DC voltage sources can be achieved by a multi-terminal transformer rectifier as shown in Figure 11 (Babaei and Kangarlu, 2012).

Figure 11.

Providing of the multiple DC voltage sources via transformer and rectifiers.

Symmetric topology

In the symmetric topology, the DC sources values are the same according to $V_{1, 1} = V_{2, 1} = V_{3, 1} = V_{1, 2} = 8 V$ as well as $V_{2, 2} = V_{3, 2} = V_{4} = V_{5} = 8 V$ . Under such conditions, the output voltage peak will be equal to 64V. Table 4 displays generation modes of different voltage levels for the proposed 17-level symmetric topology.

Table 4.

Generation modes of different voltage levels for the proposed 17-level symmetric topology.

Level	Switch states (1 = on / 0 = off)
	S_1,1	S_2,1	S_3,1	S_4,1	S_1,2	S_2,2	S_3,2	S_4,2	S₅	S₆	S₇
8	1	1	0	0	1	1	0	0	1	1	0
7	1	1	0	0	1	0	1	0	1	1	0
6	1	1	0	0	1	0	1	0	0	1	0
5	1	1	0	0	0	0	0	1	1	1	0
4	1	0	1	0	0	0	0	1	1	1	0
3	1	0	1	0	0	0	0	1	0	1	0
2	0	0	0	1	0	0	0	1	1	1	0
1	0	0	0	1	0	0	0	1	0	1	0
0	0	0	0	1	0	0	0	1	0	1	1
−1	0	0	0	1	0	0	0	1	0	0	1
−2	0	0	0	1	0	0	0	1	1	0	1
−3	1	0	1	0	0	0	0	1	0	0	1
−4	1	0	1	0	0	0	0	1	1	0	1
−5	1	1	0	0	0	0	0	1	1	0	1
−6	1	1	0	0	1	0	1	0	0	0	1
−7	1	1	0	0	1	0	1	0	1	0	1
−8	1	1	0	0	1	1	0	0	1	0	1

It should be noted that the considered values for the voltage and current are in laboratory range and these results only illustrate the capability of the proposed converter to produce the valid voltage levels and suitable feeding of the load. The proposed converter for the real applications can be easily applied for medium voltage and power ratings. Figure 12 illustrates the output voltage as well as the output current by fundamental frequency switching for the RL load. This figure indicates that the 17-level voltage waveform has steps equal to 8V and the phase difference of current versus to voltage is 45 degrees. Figure 12(a) displays simulation results and Figure 12(b) illustrates the implementation results for output voltage and load current. In Figure 12(c), the total harmonic distribution of the voltage is shown, with the THD value of 3.84% for the produced 17-level output voltage. The concordance of the simulation and implementation results is clearly visible in Figure 12.

Figure 12.

17-level output voltage and output current for the RL load in the fundamental frequency switching: (a) simulation, (b) implementation, (c) output voltage THD.

Figure 13 displays the waveforms of the generated voltage by cells 1 and 2 for symmetric topology. As can be seen in this figure, each of the proposed cells produces second and third voltage levels in symmetric source mode. Accommodations of the simulation and implementation results for the output voltage of the sub-modules are shown in Figure 13.

Figure 13.

Produced voltage in simulation and implementation of symmetric topology in cells 1 and 2: (a) first cell’s results, (b) second cell’s results.

Figure 14 demonstrates the voltage across the H-bridge module. As mentioned, the voltage applied to the H-bridge module has only positive levels and the negative voltage levels as well as the zero-voltage level are generated by switching the H-bridge switches.

Figure 14.

Voltage applied to two ends of H-bridge module in symmetric topology: (a) simulation results, (b) implementation results.

Asymmetric topology

For asymmetric topology, DC voltage source values of the second cell is considered to be twice the DC voltage source value of the first cell. In this case, six more levels will be added to the output voltage levels. In other words, the input DC voltage sources are intended according to $V_{1, 1} = V_{2, 1} = V_{3, 1} = V_{4} = V_{5} = 6 V$ and $V_{1, 2} = V_{2, 2} = V_{3, 2} = 12 V$ . With these values, the peak output voltage will be 66V.

Figure 15 displays the output voltage as well as the output load current by fundamental frequency switching method for the RL load. Figure 15(a) demonstrates the simulation results and Figure 15(b) displays the implementation results for output voltage and load current. Figure 15(c) displays the total harmonic distribution for the output voltage, which the THD value of the voltage equals to 2.85%. This figure indicates that the 23-level voltage waveform has steps equal to 6V and the proposed structure works correctly in asymmetric mode. In addition, accommodation of the simulation and implementation results can be seen in this form.

Figure 15.

23-level output voltage and RL load current: (a) simulation, (b) implementation, (c) total harmonic distribution (THD) for output voltage.

The proposed voltage waveform produced by cells 1 and 2 in asymmetric topology is illustrated in Figure 16. For considered asymmetric DC sources, proposed cell 1 generates 2nd and 3rd voltage levels and proposed cell 2 generates 4th and 6th voltage levels. The accordance of the simulation and implementation results for the generated voltage of the cell is illustrated in Figure 16.

Figure 16.

Produced voltage in proposed cells 1 and 2 in asymmetric topology: (a) first cell’s result, (b) second cell’s result.

The voltage across the H-bridge module in the asymmetric topology is demonstrated in Figure 17. According to this figure, the voltage across the H-bridge module only contains positive levels, and the negative voltage levels as well as the zero voltage level are generated by switching the H-bridge switches. The concordance of the simulation and implementation results can also be seen in this figure.

Figure 17.

Voltage across H-bridge module for asymmetric topology: (a) simulation results, (b) implementation results.

The simulation and implementation results demonstrate that the proposed structure correctly generates the desired AC voltage at two ends of the load, despite the lower count of power switches compared to other recently developed structures, and therefore can be a suitable alternative for them.

Conclusion

In this paper, a new structure for multilevel converter based on series connection of new basic cells is presented. Since the new cell produces only positive voltage levels, the proposed structure is based on the H-bridge module. The proposed structure is compared with classic structures as well as the recent multilevel structures in terms of losses and efficiency, the number of switching devices, the number of drivers, and the total blocking voltage, and is in most cases better than compared structures. Also, evaluating the TBV values for compared structures illustrates acceptable value of TBV for proposed structure. A lower number of required devices leads to the reduction of the total implementation cost of converter. In addition, the implementation and control will be simple. The performance of the proposed multilevel converter for the 17-level symmetric and 23-level asymmetric topologies is investigated. The performance of the proposed structure is clearly demonstrated by the simulation as well as the laboratory implementation.

Footnotes

Declaration of conflicting interest

The author(s) declared no potential conflicts of interest with respect to the research, authorship, and/or publication of this article.

Funding

The author(s) received no financial support for the research, authorship, and/or publication of this article.

ORCID iDs

Majid Hosseinpour

Abdolmajid Dejamkhooy

References

Abu-Rub

Holtz

Rodriguez

Baoming

(2010) Medium-voltage multilevel converters – state of the art, challenges, and requirements in industrial applications. IEEE Transactions on Industrial Electronics 57(8): 2581–2596.

Agrawal

Jain

(2017) Multilevel inverter for interfacing renewable energy sources with low/medium- and high-voltage grids. IET Renewable Power Generation 11(14): 1822–1831.

Ali

JSM

Alishah

Krishnasamy

(2019) A new generalized multilevel converter topology with reduced voltage on switches, power losses, and components. IEEE Journal of Emerging and Selected Topics in Power Electronics 7(2): 1094–1106.

Ali

JSM

Alishah

Sandeep

Hosseini

Babaei

Vijayakumar

Yaragatti

(2018) A new generalized multilevel converter topology based on cascaded connection of basic units. IEEE Journal of Emerging and Selected Topics in Power Electronics 7(4): 2498–2512.

Alishah

Hosseini

Babaei

Sabahi

(2016) A new general multilevel converter topology based on cascaded connection of submultilevel units with reduced switching components, DC sources, and blocked voltage by switches. IEEE Transactions on Industrial Electronics 63(11): 7157–7164.

Babaei

Kangarlu

(2012) Symmetric and asymmetric multilevel inverter topologies with reduced switching devices. Electric Power Systems Research 86: 122–130.

Babaei

Buccella

Saeedifard

(2016) Recent advances in multilevel inverters and their applications – part I. IEEE Transactions on Industrial Electronics 63(11): 7145–7147.

Babaei

Laali

Bayat

(2015) A single-phase cascaded multilevel inverter based on a new basic unit with reduced number of power switches. IEEE Transactions on Industrial Electronics 62(2): 922–929.

Banaei

Oskuee

MRJ

Khounjahan

(2014) Reconfiguration of semi-cascaded multilevel inverter to improve systems performance parameters. IET Power Electronics 7(5): 1106–1112.

10.

Behara

Sandeep

Yaragatti

(2018) Design and implementation of transformer-based multilevel inverter topology with reduced components. IEEE Transactions on Industry Applications 54(5): 4632–4639.

11.

Dhanamjayulu

Meikandasivam

(2018) Implementation and comparison of symmetric and asymmetric multilevel inverters for dynamic loads. IEEE Access 6: 738–746.

12.

Ebrahimi

Babaei

Gharehpetian

(2011) A new topology of cascaded multilevel converters with reduced number of components for high-voltage applications. IEEE Transactions on Power Electronics 26(11): 3109–3118.

13.

Ebrahimi

Babaei

Gharehpetian

(2012) A new multilevel converter topology with reduced number of power electronic components. IEEE Transactions on Industrial Electronics 59(2): 655–667.

14.

Flores

Dixon

Ortúzar

Carmi

Barriuso

Morán

(2008) Static VAR compensator and active power filter with power injection capability, using 27-level inverters and photovoltaic cells. IEEE Transactions on Industrial Electronics 56(1): 130–138.

15.

Geetha

Ramaswamy

(2018) New series parallel switched multilevel inverter for a three-phase induction motor. Transactions of the Institute of Measurement and Control 24(8): 1440–1454.

16.

Gupta

Jain

(2012) Topology for multilevel inverters to attain maximum number of levels from given DC sources. IET Power Electronics 5(4): 435–446.

17.

Gupta

Jain

(2013) A novel multilevel inverter based on switched DC sources. IEEE Transactions on Industrial Electronics 61(7): 3269–3278.

18.

Hosseinpour

Seifi

Dejamkhooy

Sedaghati

(2020) Switch count reduced structure for symmetric bi-directional multilevel inverter based on switch-diode-source cells. IET Power Electronics 13(8): 1675–1686.

19.

Hosseinpour

Seifi

Rahimian

(2020) A bidirectional diode containing multilevel inverter topology with reduced switch count and driver. International Journal of Circuit Theory and Applications 48(10): 1766–1785.

20.

Hsieh

Liang

Chen

Tsai

(2016) Design and implementation of a novel multilevel DC–AC inverter. IEEE Transactions on Industry Applications 52(3): 2436–2443.

21.

Jayabalan

Jeevarathinam

Sandirasegarane

(2017) Reduced switch count pulse width modulated multilevel inverter. IET Power Electronics 10(1): 10–17.

22.

Jiali

Chaoying

(2019) Hybrid modular multilevel converter with cascaded full bridges for medium-voltage motor drives. Transactions of the Institute of Measurement and Control 41(12): 3279–3291.

23.

Kangarlu

Babaei

Laali

(2012). Symmetric multilevel inverter with reduced components based on non-insulated dc voltage sources. IET Power Electronics 5(5): 571–581.

24.

Krug

Bernet

Fazel

Jalili

Malinowski

(2007) Comparison of 2.3-kV medium-voltage multilevel converters for industrial medium-voltage drives. IEEE Transactions on Industrial Electronics 54(6): 2979–2992.

25.

Majareh

SHL

Sedaghati

Hosseinpour

Mousavi-Aghdam

(2019) Design, analysis and implementation of a generalised topology for multilevel inverters with reduced circuit devices. IET Power Electronics 12(14): 3724–3731.

26.

Mohan

Undeland

Robbins

(2003) Power Electronics: Converters, Applications, and Design. New York: John Wiley & Sons.

27.

Najafi

Yatim

AHM

(2011) Design and implementation of a new multilevel inverter topology. IEEE Transactions on Industrial Electronics 59(11): 4148–4154.

28.

Oskuee

MRJ

Karimi

Ravadanegh

Gharehpetian

(2015) An innovative scheme of symmetric multilevel voltage source inverter with lower number of circuit devices. IEEE Transactions on Industrial Electronics 62(11): 6965–6973.

29.

Ounejjar

Al-Haddad

Dessaint

(2011) A novel six-band hysteresis control for the packed U cells seven-level converter: Experimental validation. IEEE Transactions on Industrial Electronics 59(10): 3808–3816.

30.

Pereda

Dixon

(2011) High-frequency link: A solution for using only one DC source in asymmetric cascaded multilevel inverters. IEEE Transactions on Industrial Electronics 58(9): 3884–3892.

31.

Saeedian

Adabi

Hosseini

(2017) Cascaded multilevel inverter based on symmetric–asymmetric DC sources with reduced number of components. IET Power Electronics 10(12): 1468–1478.

32.

Samsami

Taheri

Samanbakhsh

(2017) New bidirectional multilevel inverter topology with staircase cascading for symmetric and asymmetric structures. IET Power Electronics 10(11): 1315–1323.

33.

Sandeep

Yaragatti

(2017) A switched-capacitor-based multilevel inverter topology with reduced components. IEEE Transactions on Power Electronics 33(7): 5538–5542.

34.

Seifi

Hosseinpour

Dejamkhooy

Sedaghati

(2020) Novel reduced switch-count structure for symmetric/asymmetric cascaded multilevel inverter. Arabian Journal for Science and Engineering 45: 6687–6700.

35.

Siddique

Mekhilef

Shah

Memon

(2019) Optimal design of a new cascaded multilevel inverter topology with reduced switch count. IEEE Access 7: 24498–24510.

36.

Vahedi

Sharifzadeh

Al-Haddad

(2018) Modified seven-level pack U-cell inverter for photovoltaic applications. IEEE Journal of Emerging and Selected Topics in Power Electronics 6(3): 1508–1516.

37.

Villanueva

Correa

Rodríguez

Pacas

(2009) Control of a single-phase cascaded H-bridge multilevel inverter for grid-connected photovoltaic systems. IEEE Transactions on Industrial Electronics 56(11): 4399–4406.

38.

Yousofi-Darmian

Barakati

(2020) A new asymmetric multilevel inverter with reduced number of components. IEEE Journal of Emerging and Selected Topics in Power Electronics 8(4): 4333–4342.