A reconfigurable adder for an efficient MAC in DNNs applications on edge device

Abstract

AI devices, whether they are related to medical surgery, autonomous driving, or contactless delivery, use DNNs as an inbuilt architecture. Deployment of DNNs on resource-critical devices is still quite challenging due to huge resource requirements. Therefore, in this research paper, we propose a reconfigurable adder in the accumulation part of the MAC operation, which as a result makes DNN applications less compute intensive and lighter. A reconfigurable adder is tested in both convolution and dense parts of different DNN architectures for architecture performance and its edge deployment related matrices. In terms of architecture performance related parameters like accuracy, precision, recall, F1 score, our proposed customized architecture is quite in-line with conventional DNNs architectures (LeNet-5, AlexNet-Lite, GEMM) for three dataset MNIST, Fashion MNIST and AtoZ Handwritten. For edge deployment related matrices, our proposed architecture on CPU, reduces model size up to 61%, cpu utilization up to 50% at the expense of increasing inference time up to 36% due to minimal memory uses in architecture simulation. We also perform deployments of our proposed customized architecture (LeNet-5, AlexNet-Lite) on Jetson Nano as an edge device. Its result for parameters like cpu utilization, memory usage and model size is quite in line with software emulation of baseline architecture on CPU, inference time of our proposed architecture is 3 to 4 times as compared to the standard architecture. Jetson Nano, being a GPU supported device, works well for parallelism in comparison to sequential/parallel as our customized architecture. Higher inference time is due to trade off between terminology of architecture and supported edge devices.

Keywords

deep neural networks (DNNs)convolutional neural networks (CNNs)reconfigurable adder

Introduction

Deep neural networks (DNNs) have created huge progress in recent time and it has extended the boundaries of possible research in machine learning, computer vision and artificial intelligence. DNN Architectures such as LeNet-5, AlexNet, VGG16 and custom convolutional blocks based on General Matrix Multiplication (GEMM) are among the most popular and used models that support real time applications (Chawla, M. and Agrawal, R., 2025; Sarker, I. H., 2021). Although these models can achieve higher accuracy rates in object detection, classification and other AI applications, there remain many unresolved challenges regarding computational efficiency, especially at inference time, memory requirement and computational resources. As the models become deeper and more complex to differentiate minor features of input data, deploying these models in a limited computational resource environment becomes more challenging (Çalışkan, 2023). This situation often includes real-time systems, such as mobile applications, autonomous vehicles (Nezhadalinaei et al., 2021; Ren et al., 2021; Tuncali et al., 2018), or edge computing systems, where latency, computational energy and memory footprint play an important role (Sarker, 2019; Swapna et al., 2020). Different methods such as pruning, quantizing, and hardware accelerators have tried to address the issue, but there are still a lot of research options which are untapped yet, which can give us better results, such as approximation computing (Choi and Venkataramani, 2018; Zhang et al., 2015). In approximate computing, a neural network suffers an accuracy loss of 3% to 5% at the cost of resource efficient computation in terms of area, power saving (Dalloo et al., 2018; Gupta et al., 2012; Liang et al., 2022). This type of computation is well suited for applications in which resource requirement is at primary concern with the error-tolerant nature of application.

In this paper we have introduced the novel concept of custom reconfigurable adder in place of conventional floating point adder in MAC units. These custom reconfigurable adders start the accumulation as binary adder and perform switching between binary and conventional adder as per specific value of carry bit generated during binary accumulation operation of a customized DNN. While designing adder, the parameter which required main attention is the accumulation of previous carry with remaining bits and propagation of generated carry to the next bit. This research paper also emphasize to understand the effect of custom reconfigurable adder in both convolution (GEMMConv2D) (Pilipović et al., 2021; Su and Lei, 2018) and fully connected (Dense) layers which is implemented on LeNet-5 (Leveugle et al., 2024; Yanmei et al., 2020) and AlexNet-Lite architecture (Amanollah et al., 2023; Li et al., 2021; Shanthi and Sabeenian, 2019; Unnikrishnan et al., 2018; Xiao et al., 2017). Further the deployment of customized architecture of DNNs on edge devices needs to have proper mapping of model size and its execution parameters with edge device configurational parameters. Due to state of the art accuracy and involvement of NVIDIA’s Jetson family products in every emerging area of applications, we consider Jetson Nano as an edge device for different DNNs architecture. We are using Jetson Nano for training and inference purposes, during inference we observed that for every change in customized architecture we have to update the trained model and then deploy on the same (Parthasarathi et al., 2024). Although we are using small standard DNNs architecture and database, we do a lot of optimization.

In this paper we will discuss our extensive experiment investigation, which will provide evidence of significant reduction in model size, cpu utilization and memory usage without any significant change in model accuracy. Our work is aimed toward understanding the effectiveness and efficiency of reconfigurable adder and creating opportunities for further exploration in similar areas, in any training and inference in many different architectures. We have used the term architecture and model, ram usage and memory usage interchangeably throughout this paper. The key investigations of this research paper involves.

• Software Emulation on CPU:- We implement customized reconfigurable adder in the accumulation part of the MAC unit inside standard DNNs architecture and evaluate its performance in image classification task as compared to standard DNNs architecture and measure performance parameters.

• Software Emulation on Edge device:- Deploy customized DNNs architecture on Jetson Nano as edge device and measure performance parameters like accuracy, model size, cpu utilization, Inference time and RAM usage change.

This research paper is organized as follows: Section II provides a recent work on the complexity of DNNs as a critical parameter and tries to solve it with different techniques, further it discusses significance of multiply and accumulation operation in existing DNNs architecture and finally the importance of edge services as compared to cloud. It also discusses limitations of different language frameworks while deploying a customized DDNs architecture on edge devices. Section III discusses our proposed work and integration of reconfigurable adder in convolution and dense part of different DNNs architecture. Section IV deals with experimental setup. Section V is about results and discussion. Section VI discusses the limitations of proposed architecture. Finally, Section VII is the conclusion of our work.

Literature review and motivation

Neural network computational complexity

Research on DNNs continued over the last two decades, but due to lack of data and computing resources, it was not so trending. With the starting of ILSVRC Challenge for object recognition and image classification task in 2010 and involvement of research community, DNNs performance in object recognition and image classification task surpassed human capability for the same in 2016 (Deng et al., 2011).

DNNs, in today’s scenario, are an integral part of every AI application. It has a complex architecture due to the number of parameters (input, filters, weights, bias) and number of computation mechanisms (padding, strides, flatten, hidden layers, activation functions). The training mechanism of DNNs use a resource intensive algorithm named as back propagation, which involves the concept of partial differentiation of loss function w.r.t each weight and bias in a chain rule sequence before a new weight and bias updation (Aloysius and Geetha, 2017). Inference mechanism in deep neural networks (DNNs) consists of a sequence of matrix multiplication of input data and trained weight, followed by accumulation of the multiplication value and bias. This multiplication followed by accumulation is the MAC unit which forms the foundation of the deep neural networks. Matrix multiplication operation of MAC is quite expensive in terms of the number of clock cycles required by the processor for computation. Data precision (float32, int32, int16, int8) of input, weight and bias also play an important role in finding the memory required to store these parameters. If we consider two data for multiplication each of size N bit then the size of output will be 2N bit, the summation process, which adds several intermediate products, can be the more limiting factor with large applications, consider v is representing the no. of accumulation then size of MAC unit will be 2N + M where M = log2(v).

In the past several optimization techniques have been explored like lower data precision (float64-float32-int16), bit quantization and pruning. All of these techniques are required to reduce area, power and latency at the cost of some inference accuracy loss for error tolerable applications (Choukroun et al., 2019; Jacob et al., 2018). Pruning is a technique, which is highly explored to deploy DNNs on edge devices by removing redundant weights, layers and neurons while maintaining accuracy to a certain threshold. Data precision from float32 to int16 or int8 is also a way to reduce the model size and computational resources with the expense of degradation in accuracy. While these operations are mainly done in floating-point to provide precision. However, the precision is not important if the degradation is tolerable.

Approximate computing in neural networks

The approximate computing (Venkataramani et al., 2014) has become a common way to enable optimization of latency, power. It is a method used to improve the performance at both software and hardware level with some trade-off with accuracy in return to efficiency (Gupta et al., 2011; Jiang et al., 2015; Seo et al., 2020). Previous studies talk about the effectiveness of using approximate multiplier, approximate adder and low-precision arithmetic operation in deep learning models (Krishnamoorthi, 2018; Zhao et al., 2020). Some studies are basically focused on reducing the resource requirement in terms of less number of multiplication with help of booth multiplier, sparse multiplier and less number of addition with help of hybrid adder at the expense of accuracy of architecture. Booth multiplication is a technique which reduces the number of partial products, particularly for signed multiplication (Venkatachalam et al., 2019). Sparse multiplication deals only with the non zero bit of the multiplying digits (Greiner and Jacob, 2010). Hybrid adder is the combination of approximate adder and conventional adder, approximate adder uses less no. of gates in comparison to conventional adder so it reduces the resources requirement to implement a hybrid adder (Trivedi et al., 2023).

A lot of research papers have been published in the area of approximate computing, but there has been very little exploration done in implementing a reconfigurable adder in the DNNs layers (Ye et al., 2013). It addresses the limitation of approximate adder against accuracy and also reduces the no. of MAC operation which is indirectly represented by lower cpu utilization. To understand the benefits of reconfigurable adder and DNN architecture on real time hardware, the FPGA prototype was also explored (Hou and Chen, 2020; Kala et al., 2019; Lehnert et al., 2023; Prabakaran et al., 2018).

GEMM and dense layer bottlenecks

General Matrix Multiplication (GEMM) is often used to perform convolution, therefore it speeds up the operation by reshaping the input matrix. Although GEMM has the advantage of parallelism, the accumulation of accumulating values is still a limitation to its performance. Convolution along with dense layers are responsible for 90% of MACs operation and 80% to 90% of power consumption of a given neural network (Farrukh et al., 2020). Therefore, by carefully bounding convolution and dense layers, data can be approximated with low effect and neural network performance will improve (Nisa et al., 2018; Raghuram and Shashank, 2022; Yu et al., 2021). The sparsity of matrices is also a big hurdle which is associated with every dataset. The exploration of sparsity and use of non zero data reduces the number of MAC operations without compromising inference accuracy but it leads to higher overheads (Greiner and Jacob, 2010). To evaluate the effect of reconfigurable adder in different DNNs architecture, we applied it individually in GEMM and dense layers. In software emulation at personal computer having processing capability of i5-5200U CPU@2.20GHz, the effect of reconfigurable adder is different for both the layer with different cpu utilization, model size, memory usage and in Jetson Nano, having processing capability of quad-core ARM cortex-A57, clock frequency 1.43 GHz, we evaluate reconfigurable adder in dense part only.

Deployment of DNN model on edge devices

Deployment of DNNs on edge devices have emerged as a new domain of research. Cloud computation is a well established area in parallel to edge computing but due to latency of response in time critical application, increasing cyber security issues related to data breach at unknown client sites and privacy of data, it is more favorable to use edge computing (Meuser et al., 2024). A lot of edge devices are available and many more are in pipeline to support the demand of edge computing ex. Jetson Nano, Jetson Tx2, Pynq Z1, Raspberry Pi 3B, Edge TPU etc. Entry of tech giants like Nvidia, Meta, Google in this field creates more attractive, competitive and innovative products (Kim et al., 2020). Edge deployment of DNN models is not only limited to its deployment on microcontroller (Arduino)/microprocessor (Raspberry pi), it also supports a specialized hardware accelerator and FPGA. Every edge device with AI capability offers an inbuilt intelligence locally. It is a resource constrained computing facility which brings real time data processing with low energy and latency. Deployment of DNNs algorithm or model on edge devices required a lot of optimization, it may be in terms of size of database, architecture (No. of convolution and dense layers) and strategy to deploy (batch size, pipelining etc.) (Deng et al., 2020; Hadidi et al., 2019). Architecture optimization is the area where maximum optimization techniques have been developed, hardware management technique is one of those in which this author developed a NeuroPipe architecture which partitions neural networks into parallel subnetwork each subnetwork process by different processing unit (Kim et al., 2020). A detailed understanding of various key framework of edge devices like Darknet, Caffe, Tensorflow, Pytorch also help to optimize the performance because large models (Alexnet,VGG16) use dynamic computation graph which is easily handled by pytorch, tensorflow fails for same. There are also some library issues between google colab and Jetson nano implementation (Hadidi et al., 2019). On edge devices, processing of Neural network layer work sequentially but the operation within the layer may be in parallel or sequentially for example a convolution layer having 32 filter each of size 5 × 5 applied across an image of size 28 × 28 may kill the kernel so it is better to reduce the kernel size or perform convolution sequentially. The same treatment is application for strategy with reduced batch size and pipeline architecture. Local Computing in itself is not a big deal for deployment on edge but local computing with AI capabilities add multiple dimension of exploration like finding the minutes and hidden details of satellite image, identification and detection of hate comments on social media platform, automation of decision making in case of self driving car etc. which in return required huge resource (Deng et al., 2020; Surianarayanan et al., 2023). Keeping these limitations and meaningful research findings as a guidance, we deployed our customized DNNs architecture (LeNet-5, AlexNet-Lite) on Jetson Nano and got satisfactory results.

Motivation

The idea to work on reconfigurational adder comes from the fact that traditional addition operations in neural networks, specifically when summing convolutional output or vector-matrix products, are accurate but require unnecessary, expensive resources (Kahng and Kang, 2012). As the neural network can ignore or tolerate minor inaccuracies without degrading the performance, this allows us to replace the exact addition with a reconfigurable addition, which is lighter (Kim et al., 2013).

In literature review we went through neural network complexity as primary limitation and then approximate to reconfigurable addition in the accumulation part of MAC operations further we discussed bottlenecks of implementation of a reconfigurable adder in convolution, dense layers and finally deployment of customized architecture on the edge device. The main motive of this method is to reduce the model size, how many cycles of cpu (cpu utilization %) required to execute the trained model and memory usage which leads to easy deployment of the trained model on the edge device at the cost of higher inference time. This clearly indicates a trade-off between higher inference time and reduced resource usage.

Proposed work

Due to unending trade-off between latency, power and hardware resources of any given circuit computations, a lot of adder configurations have been proposed to make effective orchestration of these parameters of a MAC unit. Ripple carry adder has a limitation of higher delay (Shubin, 2010), Carry look ahead adder has higher complexity leads to higher power consumption, Carry save adder requires higher area and power, Kogge stone adder has high power consumption (Raju and Sa, 2017). It has been confirmed that an individual adder is not able to balance out latency, power and hardware resources of a MAC unit. Therefore, based on the merits of two adders a conditional switching between these two is preferably a better choice. Reconfigurable adder is a combination of bitwise adder and conventional full adder. It switches between both the adders based on the value of carry bit generated by AND gate and a left shift operation, which as a result decreases cpu utilization, model size, memory usage and makes an efficient MAC for DNNs application. A bitwise adder has the merit of a well structured path for accumulation on resource constrained devices. It also has a limitation of higher delay, if the carry bit is non zero in certain iterations. To solve this issue of higher delay, our algorithm traces the value of carry bit up to maximum 5 iterations, if carry bit is zero at any iteration up to 5, accumulation performed by bitwise addition. However if it is still non zero, addition operation will be performed by conventional adder. In reconfigurable adder, we are replacing conventional floating point adder with a switching path between bitwise adder and conventional floating point adder and switching activity controlled by the value of carry bit. This method we used is compatible with standard deep learning models. As the customization of proposed architecture reduces the parallelism of the algorithm. The proposed architecture represents a trade off between higher inference time and reduced resource usage particularly on the edge device like Jetson Nano, which support parallelism of algorithm efficiently.

Reconfigurable adder

At the core of our architecture is the reconfigurable adder, which produces the result of accumulation of two fixed point data in an efficient way. The main reason to choose case based switching are.

• Combining two adders and switching between them to fully exploit their positive outcomes and overcome their limitations.

• Bitwise addition (a simplest architecture with two gates and left shift operation) and floating point adder (higher accuracy).

• Bitwise addition (worst case iteration is equal to bit width) and floating point adder (complex architecture).

• To design an area efficient reconfigurable adder which as a result creates an efficient MAC.

As per the flow chart shown in Figure 1, Our Proposed method perform following steps to perform addition:

(i) Two values as an input (one value as weight and other as input sample) in a 32 bit fixed point format and it is XOR’ed at bit-level, giving an initial sum.

(ii) To get carry, both values are first gone through bitwise AND and then left shift.

(iii) Check the carry value if it is zero, initial sum, carry are final sum and carry.

(iv) If carry is non zero, start the loop, XOR’ed the initial sum and non zero carry, again calculate carry with help of bitwise AND between initial sum and non zero carry and then left shift.

(v) If during the loop iteration (in our case it is 5), carry is zero, the corresponding bitwise accumulation will be final.

(vi) After loop iteration is over, if carry value is non zero follow conventional addition.

(vii) It was tested experimentally that out of 10 vector addition, conventional adder is used in 2 cases only.

(viii) Due to power gating technique only working adders (bitwise or conventional) will be active at a time.

(xi) Experimentally, data preprocessing technique before DNNs training like weights initialization using xavier uniform creates nearly uniform distribution of trained weights around its mean value and leads to omission of bias.

(x) As we already discussed, we are working on software emulation so bitwise addition is best.

{sum}_{i + 1} = {sum}_{i} \oplus {carry}_{i}

{carry}_{i + 1} = ({sum}_{i} & {carry}_{i}) ≪ 1

Where ⊕ denotes XOR, i denotes number of iterations, & denotes AND operation, and << denotes Left-Shift.

Figure 1.

Flow chart of Reconfigurable Adder.

This approach helps us to reduce the average computation cycles of accumulation which result as an efficient MAC while preserving significant accuracy for neural inference.

Integration into CNN and dense layers

The reconfigurable adder is used into two custom TensorFlow Layers:

GEMMConv2D hybrid

In this layer, we customized the CNN part of DNNs architecture, Extracting image patches from the input image as matrices and then flattening them using extract patches and reshape, respectively. This step is continued till we get a complete image as patches or number of images as patches as per the batch size. Convert 2D kernel into 1D vector. Next, we do element-wise multiplication of input patches and kernel weights. After quantization and float to integer conversion of product value, we perform accumulation of the product value using the reconfigurable adder in place of using the floating-point summation method, if the carry bit condition is satisfied. After getting accumulation in integer value again convert it into a floating point number. The final value after MAC operation passed to the activation function. Final 1D vector again reshaped into matrix to perform further proceeding task of pooling and stride. Feature extraction with the help of the kernel is done in the CNN part and in the classification part, it is done by the dense part of the network. Figure 2 is showing the architecture of applying reconfigurable adder in the convolution layer.

Figure 2.

Working of Hybrid GEMM architecture.

Hybrid dense

In this layer, we customized dense part of DNNs architecture, input vectors received after convolution layer operation and weight matrices are firstly quantized into 32-bit integers with the help of quantization framework, and after that their products are accumulated together using the proposed reconfigurable adder, to perform bitwise addition it is necessary to convert float 32 to 32 bit fixed point integer. This basically changes the standard dot product operation into an efficient bitwise operation Figure 3. This design allows us to work with pretrained weights extracted from standard DNNs architecture and simply ignoring the bias and keeping the weight shape as usual. It ensures good performance when transferring the weight from conventional models.

Figure 3.

Working of hybrid dense layer.

Quantization method

To execute bitwise operations, we first need to quantize the input and weight value by converting them to a fixed range (usually 0–255) and casting them into 32-bit integers. After accumulation, the result is converted back to floating-point for the next layer input. This hybrid fixed-float method allows us to integrate into standard TensorFlow models without loss of possible replication capabilities. The value of acc is the multiplication of two quantized value (input and weight) in the range [0 to 255] so to convert back to floating point value, we are dividing acc value by 255*255. We also tried to cast float 32 into int16, int8, int4 respectively but due to quantization error, validation accuracy dropped significantly.

{quantized}_{input} = int 32 (x * 255)

{final}_{output} = float 32 (acc) / 255^{2}

Compatibility of layer and transferability

The two custom layers ( GEMMConv2D and Hybrid Dense) are made in such a way that they take pretrained weights from their standard layers. In case of convolution layers, reshaped kernels are copied directly, and in dense layers, we transfer only the kernel. This process is done to perform the summation in an isolated environment and compare the performance without retraining.

Experimental setup

(i) To evaluate the performance and efficacy of our reconfigurable adder, we set up a robust experimental design. Implementation was done using TensorFlow deep learning library that allows backend integration with custom layers. This environment was flexible and allowed adoption of efficient methods for utilizing our reconfigurable adder logic for both convolutional and dense layers.

(ii) All experiments were done on a CPU-only system with no GPU acceleration because we did not want to introduce performance bias. The calculation of inference time, cpu utilization, model size, memory usage is done for the inference of 10 images taken sequentially from the test dataset. We also calculated these parameters for edge device (Jetson Nano) for inference of 10, 20,40,80,160 images taken sequentially.

(iii) Performance measuring was done using psutil Python library, for real-time tracking of memory and cpu usage during inference. Similarly, inference time measurements were assessed via high-resolution timestamps done around execution of forward-passes. Critically, and before any measurements were made, all experiments were pre-warmed so that the model and TensorFlow runtime had time to initialize and therefore reduce risks of measurement bias due to lazy-loading and/or overheads from the first-time calls.

(iv) In Python TensorFlow, keras does not implement bitwise adder on actual CPU hardware, it first, mathematically simulates the behaviour of bitwise adder with the help of a lambda layer and implements it in a floating point processor as the part of the CPU.

(V) We did training and testing of the two architectures (LeNet-5, AlexNet-Lite) across two databases (MNIST, FMNIST) and extracted trained weights for the inference of customized architecture on Jetson Nano as an edge device.

Dataset

To check the robustness and generalizability of the reconfigurable adder which we proposed, we used three well-known image classification dataset that vary in terms of their degree of challenge and difference in associated input data.

MNIST

(i) Contains 70,000 images of handwritten digits (0–9) in grayscale.

(ii) Each image is in a 28 × 28 pixels format.

(iii) All dense layers are configured with reconfigurable adders.

Fashion-MNIST

(i) It contains 70,000 grayscale images of size 28 × 28 pixels.

(ii) It has 10 classes that consist of clothing items such as shirts, trousers, shoes, and bags.

(iii) The training set has 60,000 images and the test set has 10,000 images.

A-Z handwritten characters

(i) It contains 372,457 grayscale images of handwritten English uppercase alphabets (A to Z).

(ii) It includes 26 classes in which each image is in a 28 × 28 pixels format.

(iii) We have used 297,960 images as training sets and 74,491 as testing sets.

Architectures tested

GEMM-based CNN

(i) Used patch extraction and matrix multiplication as per traditional CNN convolutional layers.

(ii) The Accumulation part of all convolution layers is configured with a reconfigurable adder.

LeNet-5

(i) The standard and proposed architectures had the same convolution layers.

(ii) In the proposed architecture, we configure reconfigurable adder in all the dense layers, allowing us to measure the impact of the reconfiguration in fully-connected layers.

AlexNet-Lite

(i) Shared the original AlexNet, but was an adapted version that had equal number of layers and handled smaller input sizes and had less parameters.

(ii) Additionally, AlexNet-Lite is deeper than LeNet-5 and thus was potentially able to learn complex datasets more effectively like Fashion-MNIST and A-Z characters.

(iii) All dense layers are configured with reconfigurable adders.

Jetson Nano

Jetson Nano is a GPU-based single-board computer with a 128-core Maxwell architecture GPU and a quad-core ARM Cortex-A57 clocking at 1.43 GHz. The total available memory is 4 GB LPDDR4 with a 64-bit interface. Jetson Nano’s memory is shared between the processor and GPU.

Results and discussion

To assess the performance of our proposed reconfigurable adder, first we reviewed the performance of three existing DNNs architecture (GEMM based CNN, LeNet-5, AlexNet-Lite) and our proposed architectures with the customized layer for accumulation across three database (MNIST, FMNIST, AtoZ Handwritten) and calculate accuracy, precision, recall, F1 Score, further move to model size, cpu utilization, inference time and ram usage change. The below observations summarize trends which are clearly reflected in the tables/diagrams.

Accuracy, precision, recall, F1 score

The following observations can be drawn from the calculated parameters in Tables 1 –3.

(a) The proposed model is not biased towards any class & it has a small fraction of false positive and false negative; it means models have very less probability of wrong prediction and wrong detection.

(b) The model is well learned for the given class of classification task and high precision score indicates strong reliability of trained model.

Table 1.

Performance comparison (Standard LeNet-5 vs Proposed LeNet-5).

Dataset	Model	Acc. (%)	Prec. (%)	Recall (%)	F1 score (%)
MNIST	LeNet-5	97.99	97.97	97.97	97.97
MNIST	Prop. Lenet-5	97.95	97.9	97.93	97.93
Fashion-MNIST	LeNet-5	89.30	89.29	89.30	89.29
Fashion-MNIST	Prop. Lenet-5	89.18	89.18	89.17	89.16
AtoZ Handwritten	LeNet-5	98.10	97.45	97.49	97.47
AtoZ Handwritten	Prop. Lenet-5	98.05	97.34	97.44	97.38

Table 2.

Performance comparison (Standard AlexNet-Lite vs Proposed AlexNet-Lite).

Dataset	Model	Acc. (%)	Prec. (%)	Recall (%)	F1 score (%)
MNIST	AlexNet-Lite	98.30	98.30	98.27	98.28
MNIST	Prop. AlexNet-Lite	98.23	98.17	98.19	98.19
Fashion-MNIST	AlexNet-Lite	91.15	91.33	91.14	91.14
Fashion-MNIST	Prop. AlexNet-Lite	91.08	91.11	91.12	91.10
AtoZ Handwritten	AlexNet-Lite	98.79	98.20	98.61	98.40
AtoZ Handwritten	Prop. AlexNet-Lite	98.78	98.16	98.58	98.36

Table 3.

Performance comparison (Standard GEMM vs Proposed GEMM).

Dataset	Model	Acc. (%)	Prec. (%)	Recall (%)	F1 score (%)
MNIST	GEMM	98.27	98.27	98.24	98.25
MNIST	Prop. GEMM	98.24	96.25	98.21	98.22
Fashion-MNIST	GEMM	89.31	89.43	89.30	89.23
Fashion-MNIST	Prop. GEMM	89.26	89.38	89.26	89.18
AtoZ Handwritten	GEMM	97.91	97.60	97.08	97.32
AtoZ Handwritten	Prop. GEMM	97.85	97.57	97.09	97.34

Training and Inference on CPU (Intel i5-5200U CPU@2.20 Hz):

To get a fair comparison of all the calculated performance parameters, except the standard and proposed customized architecture everything is the same.

Inference time

Inference Time \propto {\frac{N o . o f M A C O p e r a t i o n}{C l o c k F r e q u e n c y} + M e m o r y A c c e s s T i m e}

GEMM, LeNet-5, AlexNet-Lite

As per Figures 4 –6, it is clearly stated that the inference time of our proposed architectures is higher (1.4% to 36%) w.r.t the standard architectures. As per the above formula to get a more intuitive picture of inference time, we also calculate RAM usage during inference time calculation. As per Figures 7 –9, it represents RAM usage change for the standard and proposed architectures with the same database. It is clearly understood that usage of lower RAM during proposed architectures execution is increasing memory access time which directly affects inference time calculation, ram use for LeNet-5 architecture in AtoZ Handwritten database is an exception. It is also worth noting that, if inference time is quite higher then ram usage for the same is negligible to moderate. If we combine inference time with ram usage, the effect of increased inference time is easily compensated by lower ram usage. Calculation of inference time is done on the basis of average time required to get the inference of 10 random images taken sequentially from a test dataset.

Figure 4.

Graph showing GEMM versus Proposed GEMM Architecture inference time.

Figure 5.

Graph showing Lenet-5 versus Proposed LeNet-5 Inference Time.

Figure 6.

Graph showing AlexNet-Lite versus Proposed AlexNet-Lite Inference Time.

Figure 7.

Graph showing GEMM versus Proposed GEMM Architecture RAM usage change.

Figure 8.

Graph showing Lenet-5 versus Proposed LeNet-5 RAM usage change.

Figure 9.

Graph showing AlexNet-Lite versus Proposed AlexNet-Lite RAM usage change.

CPU utilization

CPU Utilization (%) \propto {\frac{C P U E x e c u t i o n T i m e}{A l l o t t e d T i m e f o r E x e c u t i o n}}

GEMM, LeNet-5, AlexNet-Lite

As per Figures 10 –12, it is clearly stated that cpu utilization of proposed architectures decreases (6% to 54.20%) w.r.t the standard architectures. In our python code, we are calculating CPU utilization for the inference of 10 images for standard and proposed customized architecture. Therefore Allotted time for execution is same for both the architecture. This lower cpu utilization is due to efficient MAC through reconfigurable adder, pipeline accumulation and power gating technique of proposed architecture. Figures 10 –12 demonstrating the computational efficiency of lightweight bitwise operations over floating point addition.

Figure 10.

Graph showing GEMM versus Proposed GEMM CPU Usage.

Figure 11.

Graph showing Lenet-5 versus Proposed Lenet-5 CPU Usage.

Figure 12.

Graph showing AlexNet-Lite versus proposed AlexNet-Lite CPU Usage.

Model size

Model Size \propto {N o . o f T r a i n a b l e P a r a m e t e r s \times B i t w i d t h}

GEMM, LeNet-5, AlexNet-Lite

As per Figures 13 –15, it is clearly stated that the proposed architecture size is approximately 2.3 to 3 times lighter than the standard architecture. This reduction in model size is due to skipping of bias values in final accumulation leads to reducing the no. of trainable parameters and avoiding accumulation of intermediate values in serial accumulation of floating point adder. Lighter the model, it is easy to deploy on edge devices.

Figure 13.

Graph showing Model Size of GEMM versus Proposed GEMM.

Figure 14.

Graph showing Model Size of LeNet-5 versus Proposed LeNet-5.

Figure 15.

Graph showing Model Size of AlexNet-Lite versus Proposed AlexNet-Lite.

As per the results of three architectures over three databases for parameters like inference time, cpu utilization, model size, ram usage change, it is easily understood that increased inference time is due to low memory usage. Therefore reconfigurable adder is a better option for an efficient MAC for DNN applications on computing devices which have low memory.

Training and inference on Jetson Nano (quad-core ARM cortex-A57@ 1.43 GHz)

To verify edge deployment related performance of reconfigurable adder based MAC operations for DNNs applications on a resource constrained device we choose Jetson Nano (Appavu, 2025; Santos et al., 2024; Zhu et al., 2022). We trained only standard models and used their trained weights in the customized models. We tested LetNet-5, AlexNet-Lite model on MNIST and FMNIST database. We also tried to test AtoZ Handwritten database and GEMM model on the Jetson Nano but in case of AtoZ Handwritten database its size was the main constraint and customized architecture of the GEMM model needs a lot of dependencies which downgrade the performance.

Inference time

As shown in Figures 16 and 17 regarding the edge deployment of standard model and our customized model on Jetson Nano for inference time calculation. Our proposed model is not performing well, it is taking inference time approx. 3 to 4 times longer than the standard model. It is due to the following reasons

(1) We have created a standard model by using the inbuilt function of tensorflow library. All these standard functions are written with proper parallelism. In our custom architecture, we are using different functions like binary addition, flag to check carry, int to float conversion, which are not so optimized for parallelism. Jetson Nano also supports parallelism architecture better due to inbuilt default GPU support. Meanwhile the gpu accelerator works best for parallel architecture at a gain of less inference time and at a cost of higher CPU utilization and memory, compared to the architecture which is somewhere between parallel and sequential as shown in Figure 16.

(2) Parallelism of architecture supports a higher amount of memory. Therefore standard architecture is using higher memory 41% (for MNIST) and 27% (for FMNIST) in comparison to the proposed model as shown in Figure 16.

(3) Experimentally, this trade-off between resource usage and increased inference time clearly indicates the trade-off between standard (completely parallel) versus customized (parallel-sequential) architecture. If we move towards complete parallelism in our customized architecture, we are losing resource gain and customization of architecture at a cost of gain in inference time. Final selection is based on edge device architecture. Therefore choose an edge device as per the architecture of the algorithm.

Figure 16.

Graph showing Inference Time, CPU Utilization, Model Size, RAM Usage of LeNet-5 versus Proposed LeNet-5.

Figure 17.

Graph showing Inference Time, CPU Utilization, Model Size, RAM Usage of AlexNet-Lite versus Proposed AlexNet-Lite.

CPU utilization

For LeNet-5 architecture as Fig.16 on both the databases (MNIST, FMNIST), our proposed model is performing well for cpu utilization. But for AlexNet-Lite as Fig.17 the reverse is true. It is easily interpreted that our proposed model provides better cpu utilization (21.6% to 26.3%) due to efficient MAC operation, AlexNet-Lite has a number of layers that is double of LeNet-5. So our proposed model is suited for less complex architectures.

Model size

Model size is a concerning factor while designing a model for edge deployment, large size models require a large memory to store the trained weight and intermediate parameters. Model size values as shown in Fig.16, Fig.17 indicates that the proposed model is having the model size nearly half to one third of the standard model size. This reduction in model size is due to the following factors

(1) Bitwise addition of reconfigurable adder reduces the number of arithmetic operations which lead to reduction in trainable parameters.

(2) Skipping of bias values in final accumulation leads to reducing the no. of trainable parameters.

(3) Avoiding accumulation of intermediate values in serial accumulation of floating point adder.

It is to be noted that in Jetson Nano as per the hardware resource, the architecture is the primary differentiator. Our proposed architecture is laying between parallel and sequential operations which is the main drawback of edge devices like Jetson Nano which support parallelism with help of GPU.

We also compared our proposed architecture results with additional benchmarks as shown in Table 4, the authors (Baller et al., 2021; Kang and Jo, 2021; Swaminathan et al., 2025; Zhang et al., 2022) used Jetson Nano hardware as an edge device but few sets of parameters are different. For benchmark comparison of our proposed architecture, we have taken performance parameters of LeNet5 architecture deployed on Jetson Nano as shown in Figure 16. The authors (Swaminathan et al., 2025; Zhang et al., 2022) calculated inference time of the standard architecture in Tensorflow and TensorRT framework. In the Tensorflow framework, inference time of our proposed architecture is 2X of the benchmarks architectures due to lack of parallelization in the operations. TensorRT is an optimized framework of tensorflow, it works well for standard architecture but for proposed architectures, supporting libraries creates compatibility issues on Jetson Nano deployment. Accuracy of proposed architecture is better than both of the benchmark architecture (Baller et al., 2021); Kang and Jo (2021). Though, our proposed architecture is less complex as compared to the benchmark and complexity of the database also matter. However, benchmark architectures are using TensorRT, which as a result of decreasing the accuracy of classification. As per the comparison of proposed architecture with standard and benchmark architectures, it is concluded that inference time of proposed architecture is varying between 2X to 4X with better accuracy and better resource utilization. Performance parameters like CPU and Memory usage can be used as initial performance indicators.

Table 4.

Benchmarks against deployment of proposed technique on Jetson Nano.

Performance parameters		Our work		(Baller et al., 2021)	(Kang and Jo, 2021)	(Zhang et al., 2015)	(Swaminathan et al., 2025)
Performance parameters		Std.	Prop.	(Baller et al., 2021)	(Kang and Jo, 2021)	(Zhang et al., 2015)	(Swaminathan et al., 2025)
Technique		LeNet5/MNIST/Jetson nano		MobileNetV2lite/COCO/Jetson nano	InceptionV4/ImageNet/Jetson nano	Lenet-c/Handwritten digit video/Jetson nano	AlexNet/Image classification JetsonNano
Inference framework (Inference Time per Image)(s)	TensorFlow	0.3	1.2	—	—	0.600	0.6638
Inference framework (Inference Time per Image)(s)	TensorRT	—	—	0.181	0.1	0.11	0.1184
Simulated CPU Usage (%)		53.9	39.7	—	—	—	—
Memory Usage (MB)		3.4	2	2	—	—	—
Accuracy (%)		97.99	97.9	90	85	—	—

In Table 5, we are finding out performance parameters like inference time, CPU utilization, RAM usage changes while we are deploying our proposed algorithm on Jetson Nano and taking the random number of images (10, 20, 40, 80, 160) sequentially for inference purposes. In Table 5, as the number of images doubles, inference time, RAM usage change increases, but the trade-off between 3 to 4x higher inference time and 1.5 to 1.6x less RAM usage change in proposed versus standard architecture is still maintained.

Table 5.

Performance Comparison (Standard LeNet-5 vs Proposed LeNet-5) for MNIST database.

Performance Parameter	Model	No. of image sequentially for inference@ Jetson nano
No. of image	Model	10	20	40	80	160
Inference Time (Seconds)	LeNet-5	3	5.8	11	21.9	43.7
Inference Time (Seconds)	Prop. Lenet-5	12.5	19.3	33.4	63.2	125
RAM usage Change (MB)	LeNet-5	3.4	5	8	11.3	15.6
RAM usage Change (MB)	Prop. Lenet-5	2.0	3.2	5.3	7.4	10.1
CPU Utilization (%)	LeNet-5	53.9	54.7	51.4	53.1	54.50
CPU Utilization (%)	Prop. Lenet-5	39.7	40.3	37.5	41.3	38.24

CPU utilization is the time required by a process to complete execution of instructions over total allotted time. As the numbers of images increase, allotted time to perform execution increases but cpu utilization rate for our proposed architecture is lesser than standard architecture due to efficient MAC operation via reconfigurable adder. It clearly indicates that there is a trade-off between inference time and inference time versus RAM usage change, CPU utilization.

For the calculation of repeated runs, we have table number VI. In this table we are taking 20 images sequentially for inference and we are repeating it 20 times and measuring the standard deviation. On repeated runs we are getting 20 different values for each parameter. All 20 values are within the range of $\pm$ 1% to $\pm$ 2% of actual value for inference time, $\pm$ 1.7% to $\pm$ 2.5% of actual value for RAM usage change and $\pm$ 1.5% to $\pm$ 3% of actual value of CPU utilization. Standard deviation within the overall range of $\pm$ 1% to $\pm$ 3% for all parameters indicates lower margin of error and better reliability of results.

Limitations

• The deployment of the proposed model on CPU, Jetson Nano is based on software emulation.

• All the optimization in reconfigurable adder was done at algorithm level.

Conclusion

In this study, we proposed an efficient MAC architecture for deep neural networks with the help of reconfigurable adder (a software emulation based hardware friendly adder which minimized traditional floating-point accumulation), and demonstrated its efficacy. Based on the given architecture performance results using MNIST, Fashion-MNIST and AtoZ Handwritten alphabets datasets, with 3 different architectures, we found consistent performance of our proposed architectures in terms of Accuracy, Precision, Recall, F1 Score. For proposed architecture on CPU, performance parameters like cpu utilization, model size, memory usage and inference time, we are getting better performance for the first three at the expense of inference time. If we oversee inference time with ram usage change, it is clearly understood that higher inference time is due to lower ram usage. In this work we also deploy our proposed model on edge device (Jetson nano) and calculate the same parameter as above. The proposed model results with approximate 3X reduction in model size, lower cpu utilization and lower memory usage were consistently within a small margin of classification accuracy from their baseline models. Parameter like inference time is 3 to 4 times higher due to terminology of architecture and the chosen edge device supports complete parallelism. As per the comparison of proposed architecture with standard and benchmark architectures, it is concluded that inference time of proposed architecture is varying between 2X to 4X with better accuracy and better resource utilization. Performance parameters like CPU utilization and Memory usage can be used as initial performance indicators. As per Table 5, the inference time of our proposed architecture is slightly decreased as the no. of sequential images increase due to batching technique and warm-up effect. We also calculated standard deviation on repeated trials as per Table 6. The performance of our proposed model is good for all the cases except the complexity of DNNs. As the complexity of DNNs increases the performance of our proposed architecture is not up to the mark as the case of AlexNet-Lite on Jetson Nano. This work validates the use of reconfigurable arithmetic in the context of edge-based AI applications on edge devices which support sequential/parallel architecture. The proposed model presents a reasonable trade-off between terminology of architecture and inference time. Therefore, it is better to choose the edge device as per the architecture of the algorithm.

Table 6.

Calculation of Standard deviation on multiple run.

Performance Parameter	Model	Multiple run (20 times) of random image for inference@ Jetson nano
No. of image	Model	20	Standard deviation
Inference Time (Seconds)	LeNet-5	5.8	5.8 $\pm 1 % t o 2 %$
Inference Time (Seconds)	Prop. Lenet-5	19.3	19.3 $\pm 1 % t o 2 %$
RAM usage Change (MB)	LeNet-5	5	5 $\pm 1.7 % t o 2.5 %$
RAM usage Change (MB)	Prop. Lenet-5	3.2	3.2 $\pm 1.7 % t o 2.5 %$
CPU Utilization (%)	LeNet-5	54.7	54.7 $% \pm 1.5 % t o 3 %$
CPU Utilization (%)	Prop. Lenet-5	40.3	40.3 $% \pm 1.5 % t o 3 %$

Footnotes

ORCID iDs

Akash Maurya

Kamal K. Jha

Funding

The authors received no financial support for the research, authorship, and/or publication of this article.

Declaration of conflicting interests

The Authors declared no potential conflict of interest with respect to the research, authorship, and/or publication of this article.

Author biographies

Jitu Sharma received the B.Tech in Electronics & Communication Engineering in 2007 and M.Tech in digital Communication in 2012. He worked on iris recognition system as J.R.F in Gautam Buddha University, Greater Noida, India from 2013-2015. He is currently pursuing the Ph.D. degree from the Indian Institute of Information Technology Vadodara, India. His research focus is AI hardware Accelerator for edge device, Reconfigurable computing, SOC design.

Akash Maurya received the B.Tech. degree in computer science and engineering from the Indian Institute of Information Technology Vadodara, India, in 2025. He is currently pursuing the M.Tech. degree in computer science and engineering with the Indian Institute of Technology Ropar, India. His current research interests include deep learning, edge Al, data engineering, and distributed systems.

Kamal Kishor Jha is an Assistant Professor (Grade-I, Level 13A1) and Head of the Department (HoD) of Electronics and Communication Engineering at the Indian Institute of Information Technology (IIIT) Vadodara, Gandhinagar Campus, India. He received his Ph.D. and M.Tech. in VLSI Design from ABV-IIITM Gwalior in 2010 and 2015 respectively. His research expertise spans nanoelectronics, low-power VLSI design, AI hardware accelerators, machine learning, computer architecture, and energy-efficient embedded systems for medical, defence, and IoT applications.

Dharmendra Singh, Currently he has joined as Director, Indian Institute of Information Technology Vadodara and prior to this he is Senior Professor in Electronics and Communication Engineering Department, Indian Institute of Technology Roorkee, India and Joint Faculty and Former Head of Department of Computer Science and Engineering, Indian Institute of Technology Roorkee, India. He earned his Ph.D. in Electronics Engineering from IIT (BHU), Varanasi, and is a Senior Member of IEEE. He has completed over 40 sponsored projects, supervised more than 50 Ph.D. scholars, and published over 400 research papers. His research interests include Artificial Intelligence, Machine Learning, Computer Vision, Remote Sensing, Microwave Imaging, Stealth Technology, and Satellite Data Applications.

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