Abstract
The mathematical model and methods of calculation of the layout structure of comparator signal circuits with distributed parameters are presented. The algorithm of computer formulation and solving of equations of transfer functions of comparator circuits is provided. Theoretical substantiation of optimizing the micro‐layout of large‐scale integration circuits of parallel subnanosecond analog‐to‐digital converters (ADC) is proposed.
The signal modeling and investigation of transitional processes in comparator circuits of the subnanosecond range 6‐, 8‐bit ADC of different layouts are presented. It has been determined that the transitional process quality in inputs of comparator blocks strongly depends on the signal circuit layout architecture, the compatibility of wave resistances of signal microstrip lines and on the number of branches to comparator bloks.The designed layouts of the 6‐bit subnanosecond range ADC comparator circuit with different layout structures are presented. Modeling of equivalent circuits of the designed layouts was performed and the modeling results are presented.The architecture of topology for comparators circuits presented here allows the developing of gigahertz 6‐ and 8‐bit analog‐to‐digital information converter.