Direct memory access usage optimization in network applications for reduced memory latency and energy consumption

Today, wireless networks are becoming increasingly ubiquitous. Usually several complex multi-threaded applications are mapped on a single embedded system and each of them is triggered by a different input stream (in accordance with the run-time behaviours of the user and the environment). This dynamicity renders the task of fully analyzing at design-time these systems very complex, if not impossible. Therefore, run-time information has to be used in order to produce an efficient design. This introduces new challenges, especially for embedded system designers using a Direct Memory Access (DMA) module, who have to know in advance the memory transfer behaviour of the whole system, in order to design and program their DMA efficiently. This is especially important in embedded systems with DRAM memories as the concurrent accesses from different processing elements can adversely affect the page-based architecture of these memory elements. Even more, the increasingly common usage of dynamic data types further complicates the problem because the exact location of data instances in the memory is unknown at design-time. In this paper we propose a system-level optimization methodology to adapt the DMA usage parameters automatically at run-time, according to online information. With our proposed optimization approach we manage to reduce the mean latency of the memory transfers by more than 18%, thus reducing the average number of cycles that processing elements or DMAs have to waste waiting for data from the main memory, while optimizing energy consumption and system responsiveness. We evaluate our approach using a set of real-life applications and real wireless dynamic streams.